From: Jim Wilson <jimw@sifive.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Jim Wilson <jimw@sifive.com>
Subject: [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs.
Date: Tue, 29 Jan 2019 18:56:44 -0800 [thread overview]
Message-ID: <20190130025644.12754-1-jimw@sifive.com> (raw)
In-Reply-To: <CAFyWVaZ5tQq4eGaZiPBq7172PB_x3JCqV6c2xo=wSJdgbJakKQ@mail.gmail.com>
Adds a debugger field to CPURISCVState. Disable mode checks in riscv_csrrw
when true.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu.h | 3 +++
target/riscv/csr.c | 16 ++++++++--------
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743f02c..faa46d0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,6 +170,9 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+
+ /* True if in debugger mode. */
+ bool debugger;
#endif
float_status fp_status;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d1..04e6b59 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -58,7 +58,7 @@ static int ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
env->priv == PRV_S ? env->mcounteren : -1U;
- if (!(ctr_en & (1 << (csrno & 31)))) {
+ if (!env->debugger && !(ctr_en & (1 << (csrno & 31)))) {
return -1;
}
#endif
@@ -86,7 +86,7 @@ static int pmp(CPURISCVState *env, int csrno)
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -97,7 +97,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -109,7 +109,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -120,7 +120,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -132,7 +132,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -144,7 +144,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
--
2.7.4
next prev parent reply other threads:[~2019-01-30 2:57 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-30 2:49 [Qemu-devel] [PATCH 0/5 v3] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-01-30 2:54 ` [Qemu-devel] [PATCH 1/5 v3] RISC-V: Add 32-bit gdb xml files Jim Wilson
2019-02-06 23:52 ` Alistair Francis
2019-01-30 2:55 ` [Qemu-devel] [PATCH 2/5 v3] RISC-V: Add 64-bit " Jim Wilson
2019-02-06 23:53 ` Alistair Francis
2019-01-30 2:55 ` [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros Jim Wilson
2019-02-06 23:54 ` Alistair Francis
2019-01-30 2:56 ` Jim Wilson [this message]
2019-02-06 23:55 ` [Qemu-devel] [PATCH 4/5 v3] RISC-V: Add debug support for accessing CSRs Alistair Francis
2019-01-30 2:57 ` [Qemu-devel] [PATCH 5/5 v3] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2019-02-07 0:04 ` Alistair Francis
2019-02-07 2:05 ` Jim Wilson
2019-02-07 12:04 ` Richard Henderson
2019-02-08 18:16 ` Alistair Francis
2019-02-08 19:08 ` Jim Wilson
2019-02-08 19:28 ` Alistair Francis
2019-02-11 18:17 ` Palmer Dabbelt
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