From: Palmer Dabbelt <palmer@sifive.com>
To: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org,
Richard Henderson <richard.henderson@linaro.org>,
Michael Clark <mjc@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags
Date: Wed, 30 Jan 2019 09:35:52 -0800 [thread overview]
Message-ID: <20190130173601.3268-2-palmer@sifive.com> (raw)
In-Reply-To: <20190130173601.3268-1-palmer@sifive.com>
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743f02c8b95a..681341f5d5a4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_FP_ENABLE MSTATUS_FS
+#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_FP_ENABLE;
+ *flags = TB_FLAGS_MSTATUS_FS;
#else
*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 312bf298b3c2..3d07d651b60c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -44,7 +44,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
uint32_t opcode;
- uint32_t flags;
+ uint32_t mstatus_fs;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0 = NULL;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
goto do_illegal;
}
@@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->flags = ctx->base.tb->flags;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
+ ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.18.1
next prev parent reply other threads:[~2019-01-30 17:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-30 17:35 [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3 Palmer Dabbelt
2019-01-30 17:35 ` Palmer Dabbelt [this message]
2019-01-30 17:35 ` [Qemu-devel] [PULL 02/10] RISC-V: Mark mstatus.fs dirty Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 03/10] RISC-V: Implement mstatus.TSR/TW/TVM Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 04/10] RISC-V: Use riscv prefix consistently on cpu helpers Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 05/10] RISC-V: Add priv_ver to DisasContext Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 06/10] RISC-V: Add misa " Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 07/10] RISC-V: Add misa.MAFD checks to translate Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 08/10] RISC-V: Add misa runtime write support Palmer Dabbelt
2019-01-30 17:36 ` [Qemu-devel] [PULL 09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Palmer Dabbelt
2019-01-30 17:36 ` [Qemu-devel] [PULL 10/10] target/riscv: fix counter-enable checks in ctr() Palmer Dabbelt
2019-01-30 17:45 ` [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3 Eric Blake
2019-01-30 19:01 ` Palmer Dabbelt
2019-01-31 6:39 ` Thomas Huth
2019-01-31 9:51 ` Peter Maydell
2019-02-02 8:41 ` Palmer Dabbelt
2019-02-04 9:05 ` Thomas Huth
2019-02-04 9:59 ` Peter Maydell
2019-02-06 16:47 ` Palmer Dabbelt
2019-02-02 8:41 ` Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2019-02-02 9:43 [Qemu-devel] [PULL] " Palmer Dabbelt
2019-02-02 9:43 ` [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags Palmer Dabbelt
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