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From: Palmer Dabbelt <palmer@sifive.com>
To: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 05/10] RISC-V: Add priv_ver to DisasContext
Date: Wed, 30 Jan 2019 09:35:56 -0800	[thread overview]
Message-ID: <20190130173601.3268-6-palmer@sifive.com> (raw)
In-Reply-To: <20190130173601.3268-1-palmer@sifive.com>

From: Alistair Francis <Alistair.Francis@wdc.com>

The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/translate.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0581b3c1f7d7..35eb6bdfe099 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -43,6 +43,7 @@ typedef struct DisasContext {
     DisasContextBase base;
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
+    target_ulong priv_ver;
     uint32_t opcode;
     uint32_t mstatus_fs;
     uint32_t mem_idx;
@@ -1330,7 +1331,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
 #ifndef CONFIG_USER_ONLY
     /* Extract funct7 value and check whether it matches SFENCE.VMA */
     if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
-        if (env->priv_ver == PRIV_VERSION_1_10_0) {
+        if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
             /* sfence.vma */
             /* TODO: handle ASID specific fences */
             gen_helper_tlb_flush(cpu_env);
@@ -1384,7 +1385,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
             gen_helper_wfi(cpu_env);
             break;
         case 0x104: /* SFENCE.VM */
-            if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+            if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
                 gen_helper_tlb_flush(cpu_env);
             } else {
                 gen_exception_illegal(ctx);
@@ -1854,10 +1855,12 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
+    CPURISCVState *env = cs->env_ptr;
 
     ctx->pc_succ_insn = ctx->base.pc_first;
     ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
     ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+    ctx->priv_ver = env->priv_ver;
     ctx->frm = -1;  /* unknown rounding mode */
 }
 
-- 
2.18.1

  parent reply	other threads:[~2019-01-30 17:36 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-30 17:35 [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3 Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 02/10] RISC-V: Mark mstatus.fs dirty Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 03/10] RISC-V: Implement mstatus.TSR/TW/TVM Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 04/10] RISC-V: Use riscv prefix consistently on cpu helpers Palmer Dabbelt
2019-01-30 17:35 ` Palmer Dabbelt [this message]
2019-01-30 17:35 ` [Qemu-devel] [PULL 06/10] RISC-V: Add misa to DisasContext Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 07/10] RISC-V: Add misa.MAFD checks to translate Palmer Dabbelt
2019-01-30 17:35 ` [Qemu-devel] [PULL 08/10] RISC-V: Add misa runtime write support Palmer Dabbelt
2019-01-30 17:36 ` [Qemu-devel] [PULL 09/10] MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer Palmer Dabbelt
2019-01-30 17:36 ` [Qemu-devel] [PULL 10/10] target/riscv: fix counter-enable checks in ctr() Palmer Dabbelt
2019-01-30 17:45 ` [Qemu-devel] [PR RFC] RISC-V Patches for 3.2, Part 3 Eric Blake
2019-01-30 19:01   ` Palmer Dabbelt
2019-01-31  6:39     ` Thomas Huth
2019-01-31  9:51       ` Peter Maydell
2019-02-02  8:41         ` Palmer Dabbelt
2019-02-04  9:05           ` Thomas Huth
2019-02-04  9:59             ` Peter Maydell
2019-02-06 16:47               ` Palmer Dabbelt
2019-02-02  8:41       ` Palmer Dabbelt
  -- strict thread matches above, loose matches on Subject: below --
2019-02-02  9:43 [Qemu-devel] [PULL] " Palmer Dabbelt
2019-02-02  9:43 ` [Qemu-devel] [PULL 05/10] RISC-V: Add priv_ver to DisasContext Palmer Dabbelt

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