From: Martin Husemann <martin@NetBSD.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
Martin Husemann <martin@netbsd.org>
Subject: Re: [Qemu-devel] [PATCH] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI
Date: Thu, 31 Jan 2019 14:58:02 +0100 [thread overview]
Message-ID: <20190131135802.GA3213@mail.duskware.de> (raw)
In-Reply-To: <20190131130700.28392-1-peter.maydell@linaro.org>
On Thu, Jan 31, 2019 at 01:07:00PM +0000, Peter Maydell wrote:
> Martin: this is a different fix to the one I suggested you test,
> because I realized we need to make these bits RAZ/WI in the aarch32
> FPSCR as well as the aarch64 FPCR, but it should have the same effect.
This one works fine for me too.
Thanks!
Martin
next prev parent reply other threads:[~2019-01-31 13:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 13:07 [Qemu-devel] [PATCH] target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI Peter Maydell
2019-01-31 13:58 ` Martin Husemann [this message]
2019-01-31 23:04 ` Richard Henderson
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