From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/47] hw/misc/iotkit-secctl: Support 4 internal MPCs
Date: Fri, 1 Feb 2019 16:06:15 +0000 [thread overview]
Message-ID: <20190201160653.13829-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190201160653.13829-1-peter.maydell@linaro.org>
The SSE-200 has 4 banks of SRAM, each with its own internal
Memory Protection Controller. The interrupt status for these
extra MPCs appears in the same security controller SECMPCINTSTATUS
register as the MPC for the IoTKit's single SRAM bank. Enhance the
iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE
variant in use does not have all 4 MPCs then the unused inputs will
simply result in the SECMPCINTSTATUS bits being zero as required.)
The hardcoded constant "1"s in armsse.c indicate the actual number
of SRAM MPCs the IoTKit has, and will be replaced in the following
commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
---
include/hw/misc/iotkit-secctl.h | 6 +++---
hw/arm/armsse.c | 6 +++---
hw/misc/iotkit-secctl.c | 5 +++--
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h
index 1a193b306f1..bcb0437be5b 100644
--- a/include/hw/misc/iotkit-secctl.h
+++ b/include/hw/misc/iotkit-secctl.h
@@ -40,8 +40,8 @@
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
- * Controlling the MPC in the IoTKit:
- * + named GPIO input mpc_status
+ * Controlling the (up to) 4 MPCs in the IoTKit/SSE:
+ * + named GPIO inputs mpc_status[0..3]
* Controlling each of the 16 expansion MPCs which a system using the IoTKit
* might provide:
* + named GPIO inputs mpcexp_status[0..15]
@@ -67,7 +67,7 @@
#define IOTS_NUM_APB_EXP_PPC 4
#define IOTS_NUM_AHB_EXP_PPC 4
#define IOTS_NUM_EXP_MPC 16
-#define IOTS_NUM_MPC 1
+#define IOTS_NUM_MPC 4
#define IOTS_NUM_EXP_MSC 16
typedef struct IoTKitSecCtl IoTKitSecCtl;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 8554be14128..074c1d3a6cf 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -138,7 +138,7 @@ static void armsse_init(Object *obj)
sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ,
&error_abort, NULL);
- for (i = 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) {
+ for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
char *name = g_strdup_printf("mpc-irq-splitter-%d", i);
SplitIRQ *splitter = &s->mpc_irq_splitter[i];
@@ -363,7 +363,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* We must OR together lines from the MPC splitters to go to the NVIC */
object_property_set_int(OBJECT(&s->mpc_irq_orgate),
- IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", &err);
+ IOTS_NUM_EXP_MPC + 1, "num-lines", &err);
if (err) {
error_propagate(errp, err);
return;
@@ -636,7 +636,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
/* Wire up the splitters for the MPC IRQs */
- for (i = 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) {
+ for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) {
SplitIRQ *splitter = &s->mpc_irq_splitter[i];
DeviceState *dev_splitter = DEVICE(splitter);
diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c
index 2222b3e147d..537601cd53f 100644
--- a/hw/misc/iotkit-secctl.c
+++ b/hw/misc/iotkit-secctl.c
@@ -600,7 +600,7 @@ static void iotkit_secctl_mpc_status(void *opaque, int n, int level)
{
IoTKitSecCtl *s = IOTKIT_SECCTL(opaque);
- s->mpcintstatus = deposit32(s->mpcintstatus, 0, 1, !!level);
+ s->mpcintstatus = deposit32(s->mpcintstatus, n, 1, !!level);
}
static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level)
@@ -686,7 +686,8 @@ static void iotkit_secctl_init(Object *obj)
qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1);
- qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1);
+ qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status",
+ IOTS_NUM_MPC);
qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status,
"mpcexp_status", IOTS_NUM_EXP_MPC);
--
2.20.1
next prev parent reply other threads:[~2019-02-01 16:08 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 16:06 [Qemu-devel] [PULL 00/47] target-arm queue Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 08/47] hw/arm/iotkit: Rename files to hw/arm/armsse.[ch] Peter Maydell
2019-02-01 16:06 ` Peter Maydell [this message]
2019-02-01 16:06 ` [Qemu-devel] [PULL 10/47] hw/arm/armsse: Make number of SRAM banks parameterised Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 11/47] hw/arm/armsse: Make SRAM bank size configurable Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 12/47] hw/arm/armsse: Support dual-CPU configuration Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 13/47] hw/arm/armsse: Give each CPU its own view of memory Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 15/47] iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 16/47] hw/arm/armsse: Add unimplemented-device stubs for MHUs Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 17/47] hw/arm/armsse: Add unimplemented-device stubs for PPUs Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 19/47] hw/arm/armsse: Add unimplemented-device stub for CPU local " Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 20/47] hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 23/47] hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 24/47] hw/arm/mps2-tz: Add mps2-an521 model Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 25/47] target/arm/translate-a64: Don't underdecode system instructions Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 26/47] target/arm/translate-a64: Don't underdecode PRFM Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 27/47] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 28/47] target/arm/translate-a64: Don't underdecode SIMD ld/st single Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 30/47] target/arm/translate-a64: Don't underdecode FP insns Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 31/47] target/arm/translate-a64: Don't underdecode SDOT and UDOT Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 32/47] exec.c: Don't reallocate IOMMUNotifiers that are in use Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 33/47] target/arm/translate-a64: Fix FCMLA decoding error Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 34/47] target/arm/translate-a64: Fix mishandling of size in FCMLA decode Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 35/47] target/arm: Send interrupts on PMU counter overflow Peter Maydell
2020-02-25 17:08 ` Peter Maydell
2020-07-01 15:11 ` Aaron Lindsay
2020-07-03 15:14 ` Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 36/47] target/arm: Add a timer to predict " Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 37/47] target/arm: Enable API, APK bits in SCR, HCR Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 38/47] arm: Clarify the logic of set_pc() Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 39/47] target/arm: Always enable pac keys for user-only Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 40/47] aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 41/47] aarch64-linux-user: Enable HWCAP bits for PAuth Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 42/47] linux-user: Initialize aarch64 pac keys Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 43/47] target/arm: fix AArch64 virtual address space size Peter Maydell
2019-02-08 14:02 ` Laurent Vivier
2019-02-08 15:38 ` Remi Denis Courmont
2019-02-08 18:26 ` Laurent Vivier
2019-02-01 16:06 ` [Qemu-devel] [PULL 44/47] target/arm: fix decoding of B{, L}RA{A, B} Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 45/47] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 46/47] arm: Instantiate NRF51 special NVM's and NVMC Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 47/47] tests/microbit-test: Add tests for nRF51 NVMC Peter Maydell
2019-02-01 17:56 ` [Qemu-devel] [PULL 00/47] target-arm queue Peter Maydell
2019-02-03 15:00 ` no-reply
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