From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:55118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gprzA-000700-JK for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:53:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gprqD-0005oe-SK for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:44:03 -0500 Received: from mail-ed1-x541.google.com ([2a00:1450:4864:20::541]:37757) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gprqB-0005Om-Qm for qemu-devel@nongnu.org; Sat, 02 Feb 2019 04:44:00 -0500 Received: by mail-ed1-x541.google.com with SMTP id h15so7475723edb.4 for ; Sat, 02 Feb 2019 01:43:40 -0800 (PST) Date: Sat, 2 Feb 2019 01:43:20 -0800 Message-Id: <20190202094329.22874-2-palmer@sifive.com> In-Reply-To: <20190202094329.22874-1-palmer@sifive.com> References: <20190202094329.22874-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PULL 01/10] RISC-V: Split out mstatus_fs from tb_flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Michael Clark , Alistair Francis , Palmer Dabbelt From: Richard Henderson Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743f02c8b95a..681341f5d5a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 312bf298b3c2..3d07d651b60c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,7 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->pc_succ_insn = ctx->base.pc_first; - ctx->flags = ctx->base.tb->flags; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->frm = -1; /* unknown rounding mode */ } -- 2.18.1