[Qemu-devel] [PULL 0/3] target/hppa queued patches

[Qemu-devel] [PULL 0/3] target/hppa queued patches

[Richard Henderson]

One of these, unfortunately, got lost on a local branch for a year.  ;-P


r~


The following changes since commit 47994e16b1d66411953623e7c0bf0cdcd50bd507:

  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190205' into staging (2019-02-05 18:25:07 +0000)

are available in the Git repository at:

  https://github.com/rth7680/qemu.git tags/pull-hppa-20190206

for you to fetch changes up to 68aa851aa21741ab0a3c019b641d6ce72f68b3d5:

  target/hppa: fix PSW Q bit behaviour to match hardware (2019-02-06 10:49:21 +0000)

----------------------------------------------------------------
Queued target/hppa patches

----------------------------------------------------------------
Emilio G. Cota (1):
      target/hppa: use tb_cflags() to access tb->cflags

Sven Schnelle (2):
      target/hppa: fix setting registers via gdb
      target/hppa: fix PSW Q bit behaviour to match hardware

 target/hppa/gdbstub.c   |  2 +-
 target/hppa/op_helper.c | 14 +++++++++-----
 target/hppa/translate.c |  2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

[Qemu-devel] [PULL 1/3] target/hppa: use tb_cflags() to access tb->cflags

[Richard Henderson]

From: "Emilio G. Cota" <cota@braap.org>

Signed-off-by: Emilio G. Cota <cota@braap.org>
Message-Id: <1518663946-2326-1-git-send-email-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ce05d5619d..51bfd9849d 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2059,7 +2059,7 @@ static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn,
         /* FIXME: Respect PSW_S bit.  */
         nullify_over(ctx);
         tmp = dest_gpr(ctx, rt);
-        if (ctx->base.tb->cflags & CF_USE_ICOUNT) {
+        if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
             gen_io_start();
             gen_helper_read_interval_timer(tmp);
             gen_io_end();
-- 
2.17.2

[Qemu-devel] [PULL 2/3] target/hppa: fix setting registers via gdb

[Richard Henderson]

From: Sven Schnelle <svens@stackframe.org>

While doing 'set $pcoqh=0xf0000000' i triggered the assertion below.
The argument order for deposit64() is wrong, and val needs to be
moved to the end.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190128165333.3814-1-svens@stackframe.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index e2e9c4d77f..3157a690f2 100644
--- a/target/hppa/gdbstub.c
+++ b/target/hppa/gdbstub.c
@@ -266,7 +266,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     case 65 ... 127:
         {
             uint64_t *fr = &env->fr[(n - 64) / 2];
-            *fr = deposit64(*fr, val, (n & 1 ? 0 : 32), 32);
+            *fr = deposit64(*fr, (n & 1 ? 0 : 32), 32, val);
         }
         break;
     default:
-- 
2.17.2

[Qemu-devel] [PULL 3/3] target/hppa: fix PSW Q bit behaviour to match hardware

[Richard Henderson]

From: Sven Schnelle <svens@stackframe.org>

PA-RISC specification says: "Setting the PSW Q-bit, PSW{28}, to 1
with this instruction, if it was not already 1, is an undefined
operation." However, at least HP-UX 10.20 sets the Q bit from 0 to 1
with the SSM instruction. Tested this both on HP9000/712 and
HP9000/785/C3750, both machines set the Q bit from 0 to 1 without
exception. This makes HP-UX 10.20 progress a little bit further.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190129191402.29539-1-svens@stackframe.org>
[rth: Add a comment to the code as well.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/op_helper.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 912e8d5be4..6bf478e7b0 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -665,11 +665,15 @@ void HELPER(reset)(CPUHPPAState *env)
 target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
 {
     target_ulong psw = env->psw;
-    /* ??? On second reading this condition simply seems
-       to be undefined rather than a diagnosed trap.  */
-    if (nsm & ~psw & PSW_Q) {
-        hppa_dynamic_excp(env, EXCP_ILL, GETPC());
-    }
+    /*
+     * Setting the PSW Q bit to 1, if it was not already 1, is an
+     * undefined operation.
+     *
+     * However, HP-UX 10.20 does this with the SSM instruction.
+     * Tested this on HP9000/712 and HP9000/785/C3750 and both
+     * machines set the Q bit from 0 to 1 without an exception,
+     * so let this go without comment.
+     */
     env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
     return psw & PSW_SM;
 }
-- 
2.17.2

Re: [Qemu-devel] [PULL 0/3] target/hppa queued patches

[Peter Maydell]

On Wed, 6 Feb 2019 at 10:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> One of these, unfortunately, got lost on a local branch for a year.  ;-P
>
>
> r~
>
>
> The following changes since commit 47994e16b1d66411953623e7c0bf0cdcd50bd507:
>
>   Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190205' into staging (2019-02-05 18:25:07 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/rth7680/qemu.git tags/pull-hppa-20190206
>
> for you to fetch changes up to 68aa851aa21741ab0a3c019b641d6ce72f68b3d5:
>
>   target/hppa: fix PSW Q bit behaviour to match hardware (2019-02-06 10:49:21 +0000)
>
> ----------------------------------------------------------------
> Queued target/hppa patches
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM