From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:37657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05w-0005xX-9l for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05t-0000Aj-5r for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:12 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:34891) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05s-0008HQ-OM for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:08 -0500 Received: by mail-pf1-x434.google.com with SMTP id z9so4474374pfi.2 for ; Sun, 10 Feb 2019 17:08:53 -0800 (PST) From: Richard Henderson Date: Sun, 10 Feb 2019 17:08:19 -0800 Message-Id: <20190211010829.29869-17-richard.henderson@linaro.org> In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 16/26] target/arm: Implement the STGP instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 539c25a80b..9bd68d522c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2701,7 +2701,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2726,6 +2726,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2738,6 +2739,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2788,7 +2797,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + if (set_tag) { + clean_addr = new_tmp_a64(s); + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } else { + clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31); + } if (is_vector) { if (is_load) { -- 2.17.2