qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 25/26] target/arm: Enable MTE
Date: Sun, 10 Feb 2019 17:08:28 -0800	[thread overview]
Message-ID: <20190211010829.29869-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.c   | 10 ++++++++++
 target/arm/cpu64.c |  1 +
 2 files changed, 11 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index decf95de3e..a5599ae19f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -206,6 +206,16 @@ static void arm_cpu_reset(CPUState *s)
          * make no difference to the user-level emulation.
          */
         env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
+        /* Enable MTE allocation tags.  */
+        env->cp15.hcr_el2 |= HCR_ATA;
+        env->cp15.scr_el3 |= SCR_ATA;
+        env->cp15.sctlr_el[1] |= SCTLR_ATA0;
+        /* Enable synchronous tag check failures.  */
+        env->cp15.sctlr_el[1] |= 1ull << 38;
+#ifdef TARGET_AARCH64
+        /* Set MTE seed to non-zero value, otherwise RandomTag fails.  */
+        env->cp15.rgsr_el1 = 0x123400;
+#endif
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 53a7d92c95..7bd761b8f5 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -352,6 +352,7 @@ static void aarch64_max_initfn(Object *obj)
 
         t = cpu->isar.id_aa64pfr1;
         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+        t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
         cpu->isar.id_aa64pfr1 = t;
 
         t = cpu->isar.id_aa64mmfr1;
-- 
2.17.2

  parent reply	other threads:[~2019-02-11  1:09 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-11  1:08 [Qemu-devel] [PATCH v2 00/26] target/arm: Implement ARMv8.5-MemTag Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 01/26] target/arm: Split out arm_sctlr Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 02/26] target/arm: Split helper_msr_i_pstate into 3 Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 03/26] target/arm: Add clear_pstate_bits, share gen_ss_advance Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 04/26] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 05/26] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 06/26] target/arm: Add MTE system registers Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 07/26] target/arm: Assert no manual change to CACHED_PSTATE_BITS Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 08/26] target/arm: Fill in helper_mte_check Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 09/26] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 10/26] target/arm: Implement the IRG instruction Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 11/26] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 12/26] target/arm: Implement the GMI instruction Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 13/26] target/arm: Implement the SUBP instruction Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 14/26] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 15/26] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 16/26] target/arm: Implement the STGP instruction Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 17/26] target/arm: Implement the access tag cache flushes Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 18/26] target/arm: Implement data cache set allocation tags Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 19/26] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 20/26] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 21/26] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 22/26] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 23/26] target/arm: Add allocation tag storage for user mode Richard Henderson
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 24/26] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-02-11  1:08 ` Richard Henderson [this message]
2019-02-11  1:08 ` [Qemu-devel] [PATCH v2 26/26] tests/tcg/aarch64: Add mte smoke tests Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190211010829.29869-26-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).