From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:37321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gt05l-0005iu-9Q for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gt05i-0008Nk-Ed for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:09:01 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:33991) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gt05i-00083e-2s for qemu-devel@nongnu.org; Sun, 10 Feb 2019 20:08:58 -0500 Received: by mail-pf1-x444.google.com with SMTP id j18so4472061pfe.1 for ; Sun, 10 Feb 2019 17:08:39 -0800 (PST) From: Richard Henderson Date: Sun, 10 Feb 2019 17:08:08 -0800 Message-Id: <20190211010829.29869-6-richard.henderson@linaro.org> In-Reply-To: <20190211010829.29869-1-richard.henderson@linaro.org> References: <20190211010829.29869-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 05/26] target/arm: Extract TCMA with ARMVAParameters List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index e73bdbf041..cbe3500f78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10447,7 +10447,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* @@ -10462,11 +10462,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -10477,6 +10478,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -10486,6 +10488,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -10497,6 +10500,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; -- 2.17.2