From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset
Date: Mon, 11 Feb 2019 15:52:39 -0800 [thread overview]
Message-ID: <20190211235258.542-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org>
R0078 specifies that base register, or base register plus immediate
offset, is unchecked when the base register is SP.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Include writeback addresses as checked.
---
target/arm/translate-a64.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1465c52a05..27ceea66d1 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -340,11 +340,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
* This is always a fresh temporary, as we need to be able to
* increment this independently of a dirty write-back address.
*/
-static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
+static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool check)
{
TCGv_i64 clean = new_tmp_a64(s);
- if (s->mte_active) {
+ if (check && s->mte_active) {
if (s->current_el >= 2) {
/* FIXME: ARMv8.1-VHE S2 translation regime. */
gen_helper_mte_check1(clean, cpu_env, addr);
@@ -2385,7 +2385,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx,
size | MO_ALIGN | s->be_data);
}
@@ -2403,7 +2403,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
if (size == 2) {
TCGv_i64 cmp = tcg_temp_new_i64();
@@ -2528,7 +2528,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (is_lasr) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false);
return;
@@ -2537,7 +2537,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, clean_addr, size, false);
if (is_lasr) {
@@ -2557,7 +2557,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
gen_check_sp_alignment(s);
}
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
return;
@@ -2573,7 +2573,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -2587,7 +2587,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (is_lasr) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true);
return;
}
@@ -2605,7 +2605,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
s->is_ldex = true;
gen_load_exclusive(s, rt, rt2, clean_addr, size, true);
if (is_lasr) {
@@ -2795,7 +2795,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
if (!postindex) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
}
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, wback || rn != 31);
if (is_vector) {
if (is_load) {
@@ -2933,7 +2933,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
if (!post_index) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9);
}
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, writeback || rn != 31);
if (is_vector) {
if (is_store) {
@@ -3040,7 +3040,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm);
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, true);
if (is_vector) {
if (is_store) {
@@ -3125,7 +3125,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
dirty_addr = read_cpu_reg_sp(s, rn, 1);
offset = imm12 << size;
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, rn != 31);
if (is_vector) {
if (is_store) {
@@ -3209,7 +3209,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
if (rn == 31) {
gen_check_sp_alignment(s);
}
- clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+ clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn != 31);
tcg_rs = read_cpu_reg(s, rs, true);
if (o3_opc == 1) { /* LDCLR */
@@ -3271,7 +3271,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
/* Note that "clean" and "dirty" here refer to TBI not PAC. */
- clean_addr = clean_data_tbi(s, dirty_addr);
+ clean_addr = clean_data_tbi(s, dirty_addr, is_wback || rn != 31);
tcg_rt = cpu_reg(s, rt);
do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false,
@@ -3431,7 +3431,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
elements = (is_q ? 16 : 8) / ebytes;
tcg_rn = cpu_reg_sp(s, rn);
- clean_addr = clean_data_tbi(s, tcg_rn);
+ clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31);
tcg_ebytes = tcg_const_i64(ebytes);
for (r = 0; r < rpt; r++) {
@@ -3574,7 +3574,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
}
tcg_rn = cpu_reg_sp(s, rn);
- clean_addr = clean_data_tbi(s, tcg_rn);
+ clean_addr = clean_data_tbi(s, tcg_rn, is_postidx || rn != 31);
tcg_ebytes = tcg_const_i64(ebytes);
for (xs = 0; xs < selem; xs++) {
--
2.17.2
next prev parent reply other threads:[~2019-02-11 23:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-11 23:52 [Qemu-devel] [PATCH v3 00/28] target/arm: Implement ARMv8.5-MemTag Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 01/28] target/arm: Split out arm_sctlr Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 02/28] target/arm: Split helper_msr_i_pstate into 3 Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 03/28] target/arm: Add clear_pstate_bits, share gen_ss_advance Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 04/28] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 05/28] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 06/28] target/arm: Add MTE system registers Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 08/28] target/arm: Add helper_mte_check{1, 2} Richard Henderson
2019-02-11 23:52 ` Richard Henderson [this message]
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 11/28] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 12/28] target/arm: Implement the GMI instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 13/28] target/arm: Implement the SUBP instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 14/28] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 16/28] target/arm: Implement the STGP instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 19/28] target/arm: Clean address for DC ZVA Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 21/28] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 22/28] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 24/28] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 25/28] target/arm: Add allocation tag storage for user mode Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 27/28] target/arm: Enable MTE Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 28/28] tests/tcg/aarch64: Add mte smoke tests Richard Henderson
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