From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v3 12/28] target/arm: Implement the GMI instruction
Date: Mon, 11 Feb 2019 15:52:42 -0800 [thread overview]
Message-ID: <20190211235258.542-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190211235258.542-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-a64.h | 1 +
target/arm/mte_helper.c | 6 ++++++
target/arm/translate-a64.c | 6 ++++++
3 files changed, 13 insertions(+)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 6ad23bf9ee..3b78e19279 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -108,3 +108,4 @@ DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32)
DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32)
+DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 7aca5b074f..e60c6f48eb 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -220,3 +220,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr,
return address_with_allocation_tag(ptr - offset, rtag);
}
+
+uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask)
+{
+ int tag = allocation_tag_from_addr(ptr);
+ return mask | (1ULL << tag);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8e322bd6a0..791bcc3b66 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5165,6 +5165,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
gen_helper_irg(cpu_reg_sp(s, rd), cpu_env,
cpu_reg_sp(s, rn), cpu_reg(s, rm));
break;
+ case 5: /* GMI */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ }
+ gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm));
+ break;
case 8: /* LSLV */
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
break;
--
2.17.2
next prev parent reply other threads:[~2019-02-11 23:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-11 23:52 [Qemu-devel] [PATCH v3 00/28] target/arm: Implement ARMv8.5-MemTag Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 01/28] target/arm: Split out arm_sctlr Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 02/28] target/arm: Split helper_msr_i_pstate into 3 Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 03/28] target/arm: Add clear_pstate_bits, share gen_ss_advance Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 04/28] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 05/28] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 06/28] target/arm: Add MTE system registers Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 08/28] target/arm: Add helper_mte_check{1, 2} Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 11/28] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-02-11 23:52 ` Richard Henderson [this message]
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 13/28] target/arm: Implement the SUBP instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 14/28] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 16/28] target/arm: Implement the STGP instruction Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 19/28] target/arm: Clean address for DC ZVA Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 21/28] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 22/28] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 24/28] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 25/28] target/arm: Add allocation tag storage for user mode Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 27/28] target/arm: Enable MTE Richard Henderson
2019-02-11 23:52 ` [Qemu-devel] [PATCH v3 28/28] tests/tcg/aarch64: Add mte smoke tests Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190211235258.542-13-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).