From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 03/19] xive: extend the XiveRouter get_tctx() method with the page offset
Date: Tue, 12 Feb 2019 15:34:37 +1100 [thread overview]
Message-ID: <20190212043437.GK1884@umbus.fritz.box> (raw)
In-Reply-To: <20190128094625.4428-4-clg@kaod.org>
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On Mon, Jan 28, 2019 at 10:46:09AM +0100, Cédric Le Goater wrote:
> The PowerNV machine can perform indirect loads and stores on the TIMA
> on behalf of another CPU. The PIR of the CPU is controlled by a set of
> 4 registers, one per TIMA page. To know which page is being accessed,
> we need to inform the controller model of the operation offset.
This doesn't seem like the right place to handle this. Shouldn't you
instead be passing a different CPUState in for "foreign" TCTX
accesses?
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ppc/xive.h | 4 ++--
> hw/intc/spapr_xive.c | 3 ++-
> hw/intc/xive.c | 12 +++++++-----
> 3 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
> index 04d54e8315f7..a1f5ea2d9143 100644
> --- a/include/hw/ppc/xive.h
> +++ b/include/hw/ppc/xive.h
> @@ -352,7 +352,7 @@ typedef struct XiveRouterClass {
> XiveNVT *nvt);
> int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
> + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs, hwaddr offset);
> } XiveRouterClass;
>
> void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
> @@ -367,7 +367,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt);
> int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> XiveNVT *nvt, uint8_t word_number);
> -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs);
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs, hwaddr offset);
>
> /*
> * XIVE END ESBs
> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> index a0f5ff929447..c41ee96c4c84 100644
> --- a/hw/intc/spapr_xive.c
> +++ b/hw/intc/spapr_xive.c
> @@ -391,7 +391,8 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk,
> g_assert_not_reached();
> }
>
> -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs,
> + hwaddr offset)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
>
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index f5642f2338de..39dff557fadc 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -320,7 +320,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool write)
> static void xive_tm_write(void *opaque, hwaddr offset,
> uint64_t value, unsigned size)
> {
> - XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu,
> + offset);
> const XiveTmOp *xto;
>
> /*
> @@ -358,7 +359,8 @@ static void xive_tm_write(void *opaque, hwaddr offset,
>
> static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size)
> {
> - XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu);
> + XiveTCTX *tctx = xive_router_get_tctx(XIVE_ROUTER(opaque), current_cpu,
> + offset);
> const XiveTmOp *xto;
>
> /*
> @@ -1134,11 +1136,11 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
> return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number);
> }
>
> -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs)
> +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs, hwaddr offset)
> {
> XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
>
> - return xrc->get_tctx(xrtr, cs);
> + return xrc->get_tctx(xrtr, cs, offset);
> }
>
> /*
> @@ -1234,7 +1236,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format,
> */
>
> CPU_FOREACH(cs) {
> - XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs);
> + XiveTCTX *tctx = xive_router_get_tctx(xrtr, cs, 0);
> int ring;
>
> /*
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2019-02-12 5:55 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-28 9:46 [Qemu-devel] [PATCH 00/19] ppc: support for the baremetal XIVE interrupt controller (POWER9) Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 01/19] ppc/xive: hardwire the Physical CAM line of the thread context Cédric Le Goater
2019-02-08 5:44 ` David Gibson
2019-02-08 7:28 ` Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 02/19] ppc: externalize ppc_get_vcpu_by_pir() Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 03/19] xive: extend the XiveRouter get_tctx() method with the page offset Cédric Le Goater
2019-02-12 4:34 ` David Gibson [this message]
2019-02-12 8:25 ` Cédric Le Goater
2019-02-12 20:31 ` Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 04/19] ppc/pnv: xive: export the TIMA memory accessors Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 05/19] ppc/pnv: add XIVE support Cédric Le Goater
2019-02-12 5:40 ` David Gibson
2019-02-19 7:31 ` Cédric Le Goater
2019-02-21 3:13 ` David Gibson
2019-02-21 8:32 ` Cédric Le Goater
2019-03-05 3:42 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 06/19] target/ppc: Remove some #if 0'ed code Cédric Le Goater
2019-02-12 5:41 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 07/19] target/ppc: Make special ORs match x86 pause and don't generate on mttcg Cédric Le Goater
2019-02-12 5:59 ` David Gibson
2019-02-13 0:03 ` Benjamin Herrenschmidt
2019-02-13 4:54 ` David Gibson
2019-02-13 8:07 ` Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 08/19] target/ppc: Fix nip on power management instructions Cédric Le Goater
2019-02-12 6:02 ` David Gibson
2019-02-13 0:04 ` Benjamin Herrenschmidt
2019-02-15 15:30 ` Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 09/19] target/ppc: Don't clobber MSR:EE on PM instructions Cédric Le Goater
2019-02-12 6:05 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 10/19] target/ppc: Fix support for "STOP light" states on POWER9 Cédric Le Goater
2019-02-13 5:05 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 11/19] target/ppc: Move "wakeup reset" code to a separate function Cédric Le Goater
2019-02-13 5:06 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 12/19] target/ppc: Disable ISA 2.06 PM instructions on POWER9 Cédric Le Goater
2019-02-13 5:07 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 13/19] target/ppc: Rename "in_pm_state" to "resume_as_sreset" Cédric Le Goater
2019-02-13 5:08 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 14/19] target/ppc: Add POWER9 exception model Cédric Le Goater
2019-02-13 5:10 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 15/19] target/ppc: Detect erroneous condition in interrupt delivery Cédric Le Goater
2019-02-13 5:11 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 16/19] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9 Cédric Le Goater
2019-02-13 5:12 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 17/19] target/ppc: Add POWER9 external interrupt model Cédric Le Goater
2019-02-13 5:16 ` David Gibson
2019-02-15 15:43 ` Cédric Le Goater
2019-01-28 9:46 ` [Qemu-devel] [PATCH 18/19] ppc/xive: Make XIVE generate the proper interrupt types Cédric Le Goater
2019-02-13 5:17 ` David Gibson
2019-01-28 9:46 ` [Qemu-devel] [PATCH 19/19] target/ppc: Add support for LPCR:HEIC on POWER9 Cédric Le Goater
2019-02-13 5:18 ` David Gibson
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