From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:56696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtR2L-00034t-6K for qemu-devel@nongnu.org; Tue, 12 Feb 2019 00:55:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtQo2-0006eW-JY for qemu-devel@nongnu.org; Tue, 12 Feb 2019 00:40:32 -0500 Date: Tue, 12 Feb 2019 15:34:37 +1100 From: David Gibson Message-ID: <20190212043437.GK1884@umbus.fritz.box> References: <20190128094625.4428-1-clg@kaod.org> <20190128094625.4428-4-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="cEobB2knsyc5ebfU" Content-Disposition: inline In-Reply-To: <20190128094625.4428-4-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH 03/19] xive: extend the XiveRouter get_tctx() method with the page offset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org --cEobB2knsyc5ebfU Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jan 28, 2019 at 10:46:09AM +0100, C=E9dric Le Goater wrote: > The PowerNV machine can perform indirect loads and stores on the TIMA > on behalf of another CPU. The PIR of the CPU is controlled by a set of > 4 registers, one per TIMA page. To know which page is being accessed, > we need to inform the controller model of the operation offset. This doesn't seem like the right place to handle this. Shouldn't you instead be passing a different CPUState in for "foreign" TCTX accesses? >=20 > Signed-off-by: C=E9dric Le Goater > --- > include/hw/ppc/xive.h | 4 ++-- > hw/intc/spapr_xive.c | 3 ++- > hw/intc/xive.c | 12 +++++++----- > 3 files changed, 11 insertions(+), 8 deletions(-) >=20 > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h > index 04d54e8315f7..a1f5ea2d9143 100644 > --- a/include/hw/ppc/xive.h > +++ b/include/hw/ppc/xive.h > @@ -352,7 +352,7 @@ typedef struct XiveRouterClass { > XiveNVT *nvt); > int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, > XiveNVT *nvt, uint8_t word_number); > - XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs); > + XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs, hwaddr offset); > } XiveRouterClass; > =20 > void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon); > @@ -367,7 +367,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt= _blk, uint32_t nvt_idx, > XiveNVT *nvt); > int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nv= t_idx, > XiveNVT *nvt, uint8_t word_number); > -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs); > +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs, hwaddr of= fset); > =20 > /* > * XIVE END ESBs > diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c > index a0f5ff929447..c41ee96c4c84 100644 > --- a/hw/intc/spapr_xive.c > +++ b/hw/intc/spapr_xive.c > @@ -391,7 +391,8 @@ static int spapr_xive_write_nvt(XiveRouter *xrtr, uin= t8_t nvt_blk, > g_assert_not_reached(); > } > =20 > -static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) > +static XiveTCTX *spapr_xive_get_tctx(XiveRouter *xrtr, CPUState *cs, > + hwaddr offset) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > =20 > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index f5642f2338de..39dff557fadc 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -320,7 +320,8 @@ static const XiveTmOp *xive_tm_find_op(hwaddr offset,= unsigned size, bool write) > static void xive_tm_write(void *opaque, hwaddr offset, > uint64_t value, unsigned size) > { > - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current= _cpu); > + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current= _cpu, > + offset); > const XiveTmOp *xto; > =20 > /* > @@ -358,7 +359,8 @@ static void xive_tm_write(void *opaque, hwaddr offset, > =20 > static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) > { > - XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current= _cpu); > + XiveTCTX *tctx =3D xive_router_get_tctx(XIVE_ROUTER(opaque), current= _cpu, > + offset); > const XiveTmOp *xto; > =20 > /* > @@ -1134,11 +1136,11 @@ int xive_router_write_nvt(XiveRouter *xrtr, uint8= _t nvt_blk, uint32_t nvt_idx, > return xrc->write_nvt(xrtr, nvt_blk, nvt_idx, nvt, word_number); > } > =20 > -XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs) > +XiveTCTX *xive_router_get_tctx(XiveRouter *xrtr, CPUState *cs, hwaddr of= fset) > { > XiveRouterClass *xrc =3D XIVE_ROUTER_GET_CLASS(xrtr); > =20 > - return xrc->get_tctx(xrtr, cs); > + return xrc->get_tctx(xrtr, cs, offset); > } > =20 > /* > @@ -1234,7 +1236,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, = uint8_t format, > */ > =20 > CPU_FOREACH(cs) { > - XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs); > + XiveTCTX *tctx =3D xive_router_get_tctx(xrtr, cs, 0); > int ring; > =20 > /* --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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