* [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support.
@ 2019-02-12 23:04 Jim Wilson
2019-02-12 23:07 ` [Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files Jim Wilson
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:04 UTC (permalink / raw)
To: qemu-devel; +Cc: open list:RISC-V, Jim Wilson
This is the 4th version of the patch set. Updated as per the review
from Alistair, it has the riscv_csrrw_debug function added, and
Reviewed-By lines added. Otherwise it is the same as the 3rd version.
Jim
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files.
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
@ 2019-02-12 23:07 ` Jim Wilson
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 2/5] RISC-V: Add 64-bit " Jim Wilson
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:07 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++
4 files changed, 340 insertions(+)
create mode 100644 gdb-xml/riscv-32bit-cpu.xml
create mode 100644 gdb-xml/riscv-32bit-csr.xml
create mode 100644 gdb-xml/riscv-32bit-fpu.xml
diff --git a/configure b/configure
index fbd0825..febe292 100755
--- a/configure
+++ b/configure
@@ -7251,6 +7251,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml
new file mode 100644
index 0000000..c02f86c
--- /dev/null
+++ b/gdb-xml/riscv-32bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="32" type="int"/>
+ <reg name="ra" bitsize="32" type="code_ptr"/>
+ <reg name="sp" bitsize="32" type="data_ptr"/>
+ <reg name="gp" bitsize="32" type="data_ptr"/>
+ <reg name="tp" bitsize="32" type="data_ptr"/>
+ <reg name="t0" bitsize="32" type="int"/>
+ <reg name="t1" bitsize="32" type="int"/>
+ <reg name="t2" bitsize="32" type="int"/>
+ <reg name="fp" bitsize="32" type="data_ptr"/>
+ <reg name="s1" bitsize="32" type="int"/>
+ <reg name="a0" bitsize="32" type="int"/>
+ <reg name="a1" bitsize="32" type="int"/>
+ <reg name="a2" bitsize="32" type="int"/>
+ <reg name="a3" bitsize="32" type="int"/>
+ <reg name="a4" bitsize="32" type="int"/>
+ <reg name="a5" bitsize="32" type="int"/>
+ <reg name="a6" bitsize="32" type="int"/>
+ <reg name="a7" bitsize="32" type="int"/>
+ <reg name="s2" bitsize="32" type="int"/>
+ <reg name="s3" bitsize="32" type="int"/>
+ <reg name="s4" bitsize="32" type="int"/>
+ <reg name="s5" bitsize="32" type="int"/>
+ <reg name="s6" bitsize="32" type="int"/>
+ <reg name="s7" bitsize="32" type="int"/>
+ <reg name="s8" bitsize="32" type="int"/>
+ <reg name="s9" bitsize="32" type="int"/>
+ <reg name="s10" bitsize="32" type="int"/>
+ <reg name="s11" bitsize="32" type="int"/>
+ <reg name="t3" bitsize="32" type="int"/>
+ <reg name="t4" bitsize="32" type="int"/>
+ <reg name="t5" bitsize="32" type="int"/>
+ <reg name="t6" bitsize="32" type="int"/>
+ <reg name="pc" bitsize="32" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
new file mode 100644
index 0000000..4aea9e6
--- /dev/null
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="32"/>
+ <reg name="uie" bitsize="32"/>
+ <reg name="utvec" bitsize="32"/>
+ <reg name="uscratch" bitsize="32"/>
+ <reg name="uepc" bitsize="32"/>
+ <reg name="ucause" bitsize="32"/>
+ <reg name="utval" bitsize="32"/>
+ <reg name="uip" bitsize="32"/>
+ <reg name="fflags" bitsize="32"/>
+ <reg name="frm" bitsize="32"/>
+ <reg name="fcsr" bitsize="32"/>
+ <reg name="cycle" bitsize="32"/>
+ <reg name="time" bitsize="32"/>
+ <reg name="instret" bitsize="32"/>
+ <reg name="hpmcounter3" bitsize="32"/>
+ <reg name="hpmcounter4" bitsize="32"/>
+ <reg name="hpmcounter5" bitsize="32"/>
+ <reg name="hpmcounter6" bitsize="32"/>
+ <reg name="hpmcounter7" bitsize="32"/>
+ <reg name="hpmcounter8" bitsize="32"/>
+ <reg name="hpmcounter9" bitsize="32"/>
+ <reg name="hpmcounter10" bitsize="32"/>
+ <reg name="hpmcounter11" bitsize="32"/>
+ <reg name="hpmcounter12" bitsize="32"/>
+ <reg name="hpmcounter13" bitsize="32"/>
+ <reg name="hpmcounter14" bitsize="32"/>
+ <reg name="hpmcounter15" bitsize="32"/>
+ <reg name="hpmcounter16" bitsize="32"/>
+ <reg name="hpmcounter17" bitsize="32"/>
+ <reg name="hpmcounter18" bitsize="32"/>
+ <reg name="hpmcounter19" bitsize="32"/>
+ <reg name="hpmcounter20" bitsize="32"/>
+ <reg name="hpmcounter21" bitsize="32"/>
+ <reg name="hpmcounter22" bitsize="32"/>
+ <reg name="hpmcounter23" bitsize="32"/>
+ <reg name="hpmcounter24" bitsize="32"/>
+ <reg name="hpmcounter25" bitsize="32"/>
+ <reg name="hpmcounter26" bitsize="32"/>
+ <reg name="hpmcounter27" bitsize="32"/>
+ <reg name="hpmcounter28" bitsize="32"/>
+ <reg name="hpmcounter29" bitsize="32"/>
+ <reg name="hpmcounter30" bitsize="32"/>
+ <reg name="hpmcounter31" bitsize="32"/>
+ <reg name="cycleh" bitsize="32"/>
+ <reg name="timeh" bitsize="32"/>
+ <reg name="instreth" bitsize="32"/>
+ <reg name="hpmcounter3h" bitsize="32"/>
+ <reg name="hpmcounter4h" bitsize="32"/>
+ <reg name="hpmcounter5h" bitsize="32"/>
+ <reg name="hpmcounter6h" bitsize="32"/>
+ <reg name="hpmcounter7h" bitsize="32"/>
+ <reg name="hpmcounter8h" bitsize="32"/>
+ <reg name="hpmcounter9h" bitsize="32"/>
+ <reg name="hpmcounter10h" bitsize="32"/>
+ <reg name="hpmcounter11h" bitsize="32"/>
+ <reg name="hpmcounter12h" bitsize="32"/>
+ <reg name="hpmcounter13h" bitsize="32"/>
+ <reg name="hpmcounter14h" bitsize="32"/>
+ <reg name="hpmcounter15h" bitsize="32"/>
+ <reg name="hpmcounter16h" bitsize="32"/>
+ <reg name="hpmcounter17h" bitsize="32"/>
+ <reg name="hpmcounter18h" bitsize="32"/>
+ <reg name="hpmcounter19h" bitsize="32"/>
+ <reg name="hpmcounter20h" bitsize="32"/>
+ <reg name="hpmcounter21h" bitsize="32"/>
+ <reg name="hpmcounter22h" bitsize="32"/>
+ <reg name="hpmcounter23h" bitsize="32"/>
+ <reg name="hpmcounter24h" bitsize="32"/>
+ <reg name="hpmcounter25h" bitsize="32"/>
+ <reg name="hpmcounter26h" bitsize="32"/>
+ <reg name="hpmcounter27h" bitsize="32"/>
+ <reg name="hpmcounter28h" bitsize="32"/>
+ <reg name="hpmcounter29h" bitsize="32"/>
+ <reg name="hpmcounter30h" bitsize="32"/>
+ <reg name="hpmcounter31h" bitsize="32"/>
+ <reg name="sstatus" bitsize="32"/>
+ <reg name="sedeleg" bitsize="32"/>
+ <reg name="sideleg" bitsize="32"/>
+ <reg name="sie" bitsize="32"/>
+ <reg name="stvec" bitsize="32"/>
+ <reg name="scounteren" bitsize="32"/>
+ <reg name="sscratch" bitsize="32"/>
+ <reg name="sepc" bitsize="32"/>
+ <reg name="scause" bitsize="32"/>
+ <reg name="stval" bitsize="32"/>
+ <reg name="sip" bitsize="32"/>
+ <reg name="satp" bitsize="32"/>
+ <reg name="mvendorid" bitsize="32"/>
+ <reg name="marchid" bitsize="32"/>
+ <reg name="mimpid" bitsize="32"/>
+ <reg name="mhartid" bitsize="32"/>
+ <reg name="mstatus" bitsize="32"/>
+ <reg name="misa" bitsize="32"/>
+ <reg name="medeleg" bitsize="32"/>
+ <reg name="mideleg" bitsize="32"/>
+ <reg name="mie" bitsize="32"/>
+ <reg name="mtvec" bitsize="32"/>
+ <reg name="mcounteren" bitsize="32"/>
+ <reg name="mscratch" bitsize="32"/>
+ <reg name="mepc" bitsize="32"/>
+ <reg name="mcause" bitsize="32"/>
+ <reg name="mtval" bitsize="32"/>
+ <reg name="mip" bitsize="32"/>
+ <reg name="pmpcfg0" bitsize="32"/>
+ <reg name="pmpcfg1" bitsize="32"/>
+ <reg name="pmpcfg2" bitsize="32"/>
+ <reg name="pmpcfg3" bitsize="32"/>
+ <reg name="pmpaddr0" bitsize="32"/>
+ <reg name="pmpaddr1" bitsize="32"/>
+ <reg name="pmpaddr2" bitsize="32"/>
+ <reg name="pmpaddr3" bitsize="32"/>
+ <reg name="pmpaddr4" bitsize="32"/>
+ <reg name="pmpaddr5" bitsize="32"/>
+ <reg name="pmpaddr6" bitsize="32"/>
+ <reg name="pmpaddr7" bitsize="32"/>
+ <reg name="pmpaddr8" bitsize="32"/>
+ <reg name="pmpaddr9" bitsize="32"/>
+ <reg name="pmpaddr10" bitsize="32"/>
+ <reg name="pmpaddr11" bitsize="32"/>
+ <reg name="pmpaddr12" bitsize="32"/>
+ <reg name="pmpaddr13" bitsize="32"/>
+ <reg name="pmpaddr14" bitsize="32"/>
+ <reg name="pmpaddr15" bitsize="32"/>
+ <reg name="mcycle" bitsize="32"/>
+ <reg name="minstret" bitsize="32"/>
+ <reg name="mhpmcounter3" bitsize="32"/>
+ <reg name="mhpmcounter4" bitsize="32"/>
+ <reg name="mhpmcounter5" bitsize="32"/>
+ <reg name="mhpmcounter6" bitsize="32"/>
+ <reg name="mhpmcounter7" bitsize="32"/>
+ <reg name="mhpmcounter8" bitsize="32"/>
+ <reg name="mhpmcounter9" bitsize="32"/>
+ <reg name="mhpmcounter10" bitsize="32"/>
+ <reg name="mhpmcounter11" bitsize="32"/>
+ <reg name="mhpmcounter12" bitsize="32"/>
+ <reg name="mhpmcounter13" bitsize="32"/>
+ <reg name="mhpmcounter14" bitsize="32"/>
+ <reg name="mhpmcounter15" bitsize="32"/>
+ <reg name="mhpmcounter16" bitsize="32"/>
+ <reg name="mhpmcounter17" bitsize="32"/>
+ <reg name="mhpmcounter18" bitsize="32"/>
+ <reg name="mhpmcounter19" bitsize="32"/>
+ <reg name="mhpmcounter20" bitsize="32"/>
+ <reg name="mhpmcounter21" bitsize="32"/>
+ <reg name="mhpmcounter22" bitsize="32"/>
+ <reg name="mhpmcounter23" bitsize="32"/>
+ <reg name="mhpmcounter24" bitsize="32"/>
+ <reg name="mhpmcounter25" bitsize="32"/>
+ <reg name="mhpmcounter26" bitsize="32"/>
+ <reg name="mhpmcounter27" bitsize="32"/>
+ <reg name="mhpmcounter28" bitsize="32"/>
+ <reg name="mhpmcounter29" bitsize="32"/>
+ <reg name="mhpmcounter30" bitsize="32"/>
+ <reg name="mhpmcounter31" bitsize="32"/>
+ <reg name="mcycleh" bitsize="32"/>
+ <reg name="minstreth" bitsize="32"/>
+ <reg name="mhpmcounter3h" bitsize="32"/>
+ <reg name="mhpmcounter4h" bitsize="32"/>
+ <reg name="mhpmcounter5h" bitsize="32"/>
+ <reg name="mhpmcounter6h" bitsize="32"/>
+ <reg name="mhpmcounter7h" bitsize="32"/>
+ <reg name="mhpmcounter8h" bitsize="32"/>
+ <reg name="mhpmcounter9h" bitsize="32"/>
+ <reg name="mhpmcounter10h" bitsize="32"/>
+ <reg name="mhpmcounter11h" bitsize="32"/>
+ <reg name="mhpmcounter12h" bitsize="32"/>
+ <reg name="mhpmcounter13h" bitsize="32"/>
+ <reg name="mhpmcounter14h" bitsize="32"/>
+ <reg name="mhpmcounter15h" bitsize="32"/>
+ <reg name="mhpmcounter16h" bitsize="32"/>
+ <reg name="mhpmcounter17h" bitsize="32"/>
+ <reg name="mhpmcounter18h" bitsize="32"/>
+ <reg name="mhpmcounter19h" bitsize="32"/>
+ <reg name="mhpmcounter20h" bitsize="32"/>
+ <reg name="mhpmcounter21h" bitsize="32"/>
+ <reg name="mhpmcounter22h" bitsize="32"/>
+ <reg name="mhpmcounter23h" bitsize="32"/>
+ <reg name="mhpmcounter24h" bitsize="32"/>
+ <reg name="mhpmcounter25h" bitsize="32"/>
+ <reg name="mhpmcounter26h" bitsize="32"/>
+ <reg name="mhpmcounter27h" bitsize="32"/>
+ <reg name="mhpmcounter28h" bitsize="32"/>
+ <reg name="mhpmcounter29h" bitsize="32"/>
+ <reg name="mhpmcounter30h" bitsize="32"/>
+ <reg name="mhpmcounter31h" bitsize="32"/>
+ <reg name="mhpmevent3" bitsize="32"/>
+ <reg name="mhpmevent4" bitsize="32"/>
+ <reg name="mhpmevent5" bitsize="32"/>
+ <reg name="mhpmevent6" bitsize="32"/>
+ <reg name="mhpmevent7" bitsize="32"/>
+ <reg name="mhpmevent8" bitsize="32"/>
+ <reg name="mhpmevent9" bitsize="32"/>
+ <reg name="mhpmevent10" bitsize="32"/>
+ <reg name="mhpmevent11" bitsize="32"/>
+ <reg name="mhpmevent12" bitsize="32"/>
+ <reg name="mhpmevent13" bitsize="32"/>
+ <reg name="mhpmevent14" bitsize="32"/>
+ <reg name="mhpmevent15" bitsize="32"/>
+ <reg name="mhpmevent16" bitsize="32"/>
+ <reg name="mhpmevent17" bitsize="32"/>
+ <reg name="mhpmevent18" bitsize="32"/>
+ <reg name="mhpmevent19" bitsize="32"/>
+ <reg name="mhpmevent20" bitsize="32"/>
+ <reg name="mhpmevent21" bitsize="32"/>
+ <reg name="mhpmevent22" bitsize="32"/>
+ <reg name="mhpmevent23" bitsize="32"/>
+ <reg name="mhpmevent24" bitsize="32"/>
+ <reg name="mhpmevent25" bitsize="32"/>
+ <reg name="mhpmevent26" bitsize="32"/>
+ <reg name="mhpmevent27" bitsize="32"/>
+ <reg name="mhpmevent28" bitsize="32"/>
+ <reg name="mhpmevent29" bitsize="32"/>
+ <reg name="mhpmevent30" bitsize="32"/>
+ <reg name="mhpmevent31" bitsize="32"/>
+ <reg name="tselect" bitsize="32"/>
+ <reg name="tdata1" bitsize="32"/>
+ <reg name="tdata2" bitsize="32"/>
+ <reg name="tdata3" bitsize="32"/>
+ <reg name="dcsr" bitsize="32"/>
+ <reg name="dpc" bitsize="32"/>
+ <reg name="dscratch" bitsize="32"/>
+ <reg name="hstatus" bitsize="32"/>
+ <reg name="hedeleg" bitsize="32"/>
+ <reg name="hideleg" bitsize="32"/>
+ <reg name="hie" bitsize="32"/>
+ <reg name="htvec" bitsize="32"/>
+ <reg name="hscratch" bitsize="32"/>
+ <reg name="hepc" bitsize="32"/>
+ <reg name="hcause" bitsize="32"/>
+ <reg name="hbadaddr" bitsize="32"/>
+ <reg name="hip" bitsize="32"/>
+ <reg name="mbase" bitsize="32"/>
+ <reg name="mbound" bitsize="32"/>
+ <reg name="mibase" bitsize="32"/>
+ <reg name="mibound" bitsize="32"/>
+ <reg name="mdbase" bitsize="32"/>
+ <reg name="mdbound" bitsize="32"/>
+ <reg name="mucounteren" bitsize="32"/>
+ <reg name="mscounteren" bitsize="32"/>
+ <reg name="mhcounteren" bitsize="32"/>
+</feature>
diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml
new file mode 100644
index 0000000..783287d
--- /dev/null
+++ b/gdb-xml/riscv-32bit-fpu.xml
@@ -0,0 +1,46 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+ <reg name="ft0" bitsize="32" type="ieee_single"/>
+ <reg name="ft1" bitsize="32" type="ieee_single"/>
+ <reg name="ft2" bitsize="32" type="ieee_single"/>
+ <reg name="ft3" bitsize="32" type="ieee_single"/>
+ <reg name="ft4" bitsize="32" type="ieee_single"/>
+ <reg name="ft5" bitsize="32" type="ieee_single"/>
+ <reg name="ft6" bitsize="32" type="ieee_single"/>
+ <reg name="ft7" bitsize="32" type="ieee_single"/>
+ <reg name="fs0" bitsize="32" type="ieee_single"/>
+ <reg name="fs1" bitsize="32" type="ieee_single"/>
+ <reg name="fa0" bitsize="32" type="ieee_single"/>
+ <reg name="fa1" bitsize="32" type="ieee_single"/>
+ <reg name="fa2" bitsize="32" type="ieee_single"/>
+ <reg name="fa3" bitsize="32" type="ieee_single"/>
+ <reg name="fa4" bitsize="32" type="ieee_single"/>
+ <reg name="fa5" bitsize="32" type="ieee_single"/>
+ <reg name="fa6" bitsize="32" type="ieee_single"/>
+ <reg name="fa7" bitsize="32" type="ieee_single"/>
+ <reg name="fs2" bitsize="32" type="ieee_single"/>
+ <reg name="fs3" bitsize="32" type="ieee_single"/>
+ <reg name="fs4" bitsize="32" type="ieee_single"/>
+ <reg name="fs5" bitsize="32" type="ieee_single"/>
+ <reg name="fs6" bitsize="32" type="ieee_single"/>
+ <reg name="fs7" bitsize="32" type="ieee_single"/>
+ <reg name="fs8" bitsize="32" type="ieee_single"/>
+ <reg name="fs9" bitsize="32" type="ieee_single"/>
+ <reg name="fs10" bitsize="32" type="ieee_single"/>
+ <reg name="fs11" bitsize="32" type="ieee_single"/>
+ <reg name="ft8" bitsize="32" type="ieee_single"/>
+ <reg name="ft9" bitsize="32" type="ieee_single"/>
+ <reg name="ft10" bitsize="32" type="ieee_single"/>
+ <reg name="ft11" bitsize="32" type="ieee_single"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 2/5] RISC-V: Add 64-bit gdb xml files.
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-02-12 23:07 ` [Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files Jim Wilson
@ 2019-02-12 23:08 ` Jim Wilson
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros Jim Wilson
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:08 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++
gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++++++
gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++
4 files changed, 346 insertions(+)
create mode 100644 gdb-xml/riscv-64bit-cpu.xml
create mode 100644 gdb-xml/riscv-64bit-csr.xml
create mode 100644 gdb-xml/riscv-64bit-fpu.xml
diff --git a/configure b/configure
index febe292..d7cae4e 100755
--- a/configure
+++ b/configure
@@ -7258,6 +7258,7 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
+ gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml
new file mode 100644
index 0000000..f37d7f3
--- /dev/null
+++ b/gdb-xml/riscv-64bit-cpu.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml
new file mode 100644
index 0000000..a3de834
--- /dev/null
+++ b/gdb-xml/riscv-64bit-csr.xml
@@ -0,0 +1,250 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.csr">
+ <reg name="ustatus" bitsize="64"/>
+ <reg name="uie" bitsize="64"/>
+ <reg name="utvec" bitsize="64"/>
+ <reg name="uscratch" bitsize="64"/>
+ <reg name="uepc" bitsize="64"/>
+ <reg name="ucause" bitsize="64"/>
+ <reg name="utval" bitsize="64"/>
+ <reg name="uip" bitsize="64"/>
+ <reg name="fflags" bitsize="64"/>
+ <reg name="frm" bitsize="64"/>
+ <reg name="fcsr" bitsize="64"/>
+ <reg name="cycle" bitsize="64"/>
+ <reg name="time" bitsize="64"/>
+ <reg name="instret" bitsize="64"/>
+ <reg name="hpmcounter3" bitsize="64"/>
+ <reg name="hpmcounter4" bitsize="64"/>
+ <reg name="hpmcounter5" bitsize="64"/>
+ <reg name="hpmcounter6" bitsize="64"/>
+ <reg name="hpmcounter7" bitsize="64"/>
+ <reg name="hpmcounter8" bitsize="64"/>
+ <reg name="hpmcounter9" bitsize="64"/>
+ <reg name="hpmcounter10" bitsize="64"/>
+ <reg name="hpmcounter11" bitsize="64"/>
+ <reg name="hpmcounter12" bitsize="64"/>
+ <reg name="hpmcounter13" bitsize="64"/>
+ <reg name="hpmcounter14" bitsize="64"/>
+ <reg name="hpmcounter15" bitsize="64"/>
+ <reg name="hpmcounter16" bitsize="64"/>
+ <reg name="hpmcounter17" bitsize="64"/>
+ <reg name="hpmcounter18" bitsize="64"/>
+ <reg name="hpmcounter19" bitsize="64"/>
+ <reg name="hpmcounter20" bitsize="64"/>
+ <reg name="hpmcounter21" bitsize="64"/>
+ <reg name="hpmcounter22" bitsize="64"/>
+ <reg name="hpmcounter23" bitsize="64"/>
+ <reg name="hpmcounter24" bitsize="64"/>
+ <reg name="hpmcounter25" bitsize="64"/>
+ <reg name="hpmcounter26" bitsize="64"/>
+ <reg name="hpmcounter27" bitsize="64"/>
+ <reg name="hpmcounter28" bitsize="64"/>
+ <reg name="hpmcounter29" bitsize="64"/>
+ <reg name="hpmcounter30" bitsize="64"/>
+ <reg name="hpmcounter31" bitsize="64"/>
+ <reg name="cycleh" bitsize="64"/>
+ <reg name="timeh" bitsize="64"/>
+ <reg name="instreth" bitsize="64"/>
+ <reg name="hpmcounter3h" bitsize="64"/>
+ <reg name="hpmcounter4h" bitsize="64"/>
+ <reg name="hpmcounter5h" bitsize="64"/>
+ <reg name="hpmcounter6h" bitsize="64"/>
+ <reg name="hpmcounter7h" bitsize="64"/>
+ <reg name="hpmcounter8h" bitsize="64"/>
+ <reg name="hpmcounter9h" bitsize="64"/>
+ <reg name="hpmcounter10h" bitsize="64"/>
+ <reg name="hpmcounter11h" bitsize="64"/>
+ <reg name="hpmcounter12h" bitsize="64"/>
+ <reg name="hpmcounter13h" bitsize="64"/>
+ <reg name="hpmcounter14h" bitsize="64"/>
+ <reg name="hpmcounter15h" bitsize="64"/>
+ <reg name="hpmcounter16h" bitsize="64"/>
+ <reg name="hpmcounter17h" bitsize="64"/>
+ <reg name="hpmcounter18h" bitsize="64"/>
+ <reg name="hpmcounter19h" bitsize="64"/>
+ <reg name="hpmcounter20h" bitsize="64"/>
+ <reg name="hpmcounter21h" bitsize="64"/>
+ <reg name="hpmcounter22h" bitsize="64"/>
+ <reg name="hpmcounter23h" bitsize="64"/>
+ <reg name="hpmcounter24h" bitsize="64"/>
+ <reg name="hpmcounter25h" bitsize="64"/>
+ <reg name="hpmcounter26h" bitsize="64"/>
+ <reg name="hpmcounter27h" bitsize="64"/>
+ <reg name="hpmcounter28h" bitsize="64"/>
+ <reg name="hpmcounter29h" bitsize="64"/>
+ <reg name="hpmcounter30h" bitsize="64"/>
+ <reg name="hpmcounter31h" bitsize="64"/>
+ <reg name="sstatus" bitsize="64"/>
+ <reg name="sedeleg" bitsize="64"/>
+ <reg name="sideleg" bitsize="64"/>
+ <reg name="sie" bitsize="64"/>
+ <reg name="stvec" bitsize="64"/>
+ <reg name="scounteren" bitsize="64"/>
+ <reg name="sscratch" bitsize="64"/>
+ <reg name="sepc" bitsize="64"/>
+ <reg name="scause" bitsize="64"/>
+ <reg name="stval" bitsize="64"/>
+ <reg name="sip" bitsize="64"/>
+ <reg name="satp" bitsize="64"/>
+ <reg name="mvendorid" bitsize="64"/>
+ <reg name="marchid" bitsize="64"/>
+ <reg name="mimpid" bitsize="64"/>
+ <reg name="mhartid" bitsize="64"/>
+ <reg name="mstatus" bitsize="64"/>
+ <reg name="misa" bitsize="64"/>
+ <reg name="medeleg" bitsize="64"/>
+ <reg name="mideleg" bitsize="64"/>
+ <reg name="mie" bitsize="64"/>
+ <reg name="mtvec" bitsize="64"/>
+ <reg name="mcounteren" bitsize="64"/>
+ <reg name="mscratch" bitsize="64"/>
+ <reg name="mepc" bitsize="64"/>
+ <reg name="mcause" bitsize="64"/>
+ <reg name="mtval" bitsize="64"/>
+ <reg name="mip" bitsize="64"/>
+ <reg name="pmpcfg0" bitsize="64"/>
+ <reg name="pmpcfg1" bitsize="64"/>
+ <reg name="pmpcfg2" bitsize="64"/>
+ <reg name="pmpcfg3" bitsize="64"/>
+ <reg name="pmpaddr0" bitsize="64"/>
+ <reg name="pmpaddr1" bitsize="64"/>
+ <reg name="pmpaddr2" bitsize="64"/>
+ <reg name="pmpaddr3" bitsize="64"/>
+ <reg name="pmpaddr4" bitsize="64"/>
+ <reg name="pmpaddr5" bitsize="64"/>
+ <reg name="pmpaddr6" bitsize="64"/>
+ <reg name="pmpaddr7" bitsize="64"/>
+ <reg name="pmpaddr8" bitsize="64"/>
+ <reg name="pmpaddr9" bitsize="64"/>
+ <reg name="pmpaddr10" bitsize="64"/>
+ <reg name="pmpaddr11" bitsize="64"/>
+ <reg name="pmpaddr12" bitsize="64"/>
+ <reg name="pmpaddr13" bitsize="64"/>
+ <reg name="pmpaddr14" bitsize="64"/>
+ <reg name="pmpaddr15" bitsize="64"/>
+ <reg name="mcycle" bitsize="64"/>
+ <reg name="minstret" bitsize="64"/>
+ <reg name="mhpmcounter3" bitsize="64"/>
+ <reg name="mhpmcounter4" bitsize="64"/>
+ <reg name="mhpmcounter5" bitsize="64"/>
+ <reg name="mhpmcounter6" bitsize="64"/>
+ <reg name="mhpmcounter7" bitsize="64"/>
+ <reg name="mhpmcounter8" bitsize="64"/>
+ <reg name="mhpmcounter9" bitsize="64"/>
+ <reg name="mhpmcounter10" bitsize="64"/>
+ <reg name="mhpmcounter11" bitsize="64"/>
+ <reg name="mhpmcounter12" bitsize="64"/>
+ <reg name="mhpmcounter13" bitsize="64"/>
+ <reg name="mhpmcounter14" bitsize="64"/>
+ <reg name="mhpmcounter15" bitsize="64"/>
+ <reg name="mhpmcounter16" bitsize="64"/>
+ <reg name="mhpmcounter17" bitsize="64"/>
+ <reg name="mhpmcounter18" bitsize="64"/>
+ <reg name="mhpmcounter19" bitsize="64"/>
+ <reg name="mhpmcounter20" bitsize="64"/>
+ <reg name="mhpmcounter21" bitsize="64"/>
+ <reg name="mhpmcounter22" bitsize="64"/>
+ <reg name="mhpmcounter23" bitsize="64"/>
+ <reg name="mhpmcounter24" bitsize="64"/>
+ <reg name="mhpmcounter25" bitsize="64"/>
+ <reg name="mhpmcounter26" bitsize="64"/>
+ <reg name="mhpmcounter27" bitsize="64"/>
+ <reg name="mhpmcounter28" bitsize="64"/>
+ <reg name="mhpmcounter29" bitsize="64"/>
+ <reg name="mhpmcounter30" bitsize="64"/>
+ <reg name="mhpmcounter31" bitsize="64"/>
+ <reg name="mcycleh" bitsize="64"/>
+ <reg name="minstreth" bitsize="64"/>
+ <reg name="mhpmcounter3h" bitsize="64"/>
+ <reg name="mhpmcounter4h" bitsize="64"/>
+ <reg name="mhpmcounter5h" bitsize="64"/>
+ <reg name="mhpmcounter6h" bitsize="64"/>
+ <reg name="mhpmcounter7h" bitsize="64"/>
+ <reg name="mhpmcounter8h" bitsize="64"/>
+ <reg name="mhpmcounter9h" bitsize="64"/>
+ <reg name="mhpmcounter10h" bitsize="64"/>
+ <reg name="mhpmcounter11h" bitsize="64"/>
+ <reg name="mhpmcounter12h" bitsize="64"/>
+ <reg name="mhpmcounter13h" bitsize="64"/>
+ <reg name="mhpmcounter14h" bitsize="64"/>
+ <reg name="mhpmcounter15h" bitsize="64"/>
+ <reg name="mhpmcounter16h" bitsize="64"/>
+ <reg name="mhpmcounter17h" bitsize="64"/>
+ <reg name="mhpmcounter18h" bitsize="64"/>
+ <reg name="mhpmcounter19h" bitsize="64"/>
+ <reg name="mhpmcounter20h" bitsize="64"/>
+ <reg name="mhpmcounter21h" bitsize="64"/>
+ <reg name="mhpmcounter22h" bitsize="64"/>
+ <reg name="mhpmcounter23h" bitsize="64"/>
+ <reg name="mhpmcounter24h" bitsize="64"/>
+ <reg name="mhpmcounter25h" bitsize="64"/>
+ <reg name="mhpmcounter26h" bitsize="64"/>
+ <reg name="mhpmcounter27h" bitsize="64"/>
+ <reg name="mhpmcounter28h" bitsize="64"/>
+ <reg name="mhpmcounter29h" bitsize="64"/>
+ <reg name="mhpmcounter30h" bitsize="64"/>
+ <reg name="mhpmcounter31h" bitsize="64"/>
+ <reg name="mhpmevent3" bitsize="64"/>
+ <reg name="mhpmevent4" bitsize="64"/>
+ <reg name="mhpmevent5" bitsize="64"/>
+ <reg name="mhpmevent6" bitsize="64"/>
+ <reg name="mhpmevent7" bitsize="64"/>
+ <reg name="mhpmevent8" bitsize="64"/>
+ <reg name="mhpmevent9" bitsize="64"/>
+ <reg name="mhpmevent10" bitsize="64"/>
+ <reg name="mhpmevent11" bitsize="64"/>
+ <reg name="mhpmevent12" bitsize="64"/>
+ <reg name="mhpmevent13" bitsize="64"/>
+ <reg name="mhpmevent14" bitsize="64"/>
+ <reg name="mhpmevent15" bitsize="64"/>
+ <reg name="mhpmevent16" bitsize="64"/>
+ <reg name="mhpmevent17" bitsize="64"/>
+ <reg name="mhpmevent18" bitsize="64"/>
+ <reg name="mhpmevent19" bitsize="64"/>
+ <reg name="mhpmevent20" bitsize="64"/>
+ <reg name="mhpmevent21" bitsize="64"/>
+ <reg name="mhpmevent22" bitsize="64"/>
+ <reg name="mhpmevent23" bitsize="64"/>
+ <reg name="mhpmevent24" bitsize="64"/>
+ <reg name="mhpmevent25" bitsize="64"/>
+ <reg name="mhpmevent26" bitsize="64"/>
+ <reg name="mhpmevent27" bitsize="64"/>
+ <reg name="mhpmevent28" bitsize="64"/>
+ <reg name="mhpmevent29" bitsize="64"/>
+ <reg name="mhpmevent30" bitsize="64"/>
+ <reg name="mhpmevent31" bitsize="64"/>
+ <reg name="tselect" bitsize="64"/>
+ <reg name="tdata1" bitsize="64"/>
+ <reg name="tdata2" bitsize="64"/>
+ <reg name="tdata3" bitsize="64"/>
+ <reg name="dcsr" bitsize="64"/>
+ <reg name="dpc" bitsize="64"/>
+ <reg name="dscratch" bitsize="64"/>
+ <reg name="hstatus" bitsize="64"/>
+ <reg name="hedeleg" bitsize="64"/>
+ <reg name="hideleg" bitsize="64"/>
+ <reg name="hie" bitsize="64"/>
+ <reg name="htvec" bitsize="64"/>
+ <reg name="hscratch" bitsize="64"/>
+ <reg name="hepc" bitsize="64"/>
+ <reg name="hcause" bitsize="64"/>
+ <reg name="hbadaddr" bitsize="64"/>
+ <reg name="hip" bitsize="64"/>
+ <reg name="mbase" bitsize="64"/>
+ <reg name="mbound" bitsize="64"/>
+ <reg name="mibase" bitsize="64"/>
+ <reg name="mibound" bitsize="64"/>
+ <reg name="mdbase" bitsize="64"/>
+ <reg name="mdbound" bitsize="64"/>
+ <reg name="mucounteren" bitsize="64"/>
+ <reg name="mscounteren" bitsize="64"/>
+ <reg name="mhcounteren" bitsize="64"/>
+</feature>
diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml
new file mode 100644
index 0000000..fb24b72
--- /dev/null
+++ b/gdb-xml/riscv-64bit-fpu.xml
@@ -0,0 +1,52 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.riscv.fpu">
+
+ <union id="riscv_double">
+ <field name="float" type="ieee_single"/>
+ <field name="double" type="ieee_double"/>
+ </union>
+
+ <reg name="ft0" bitsize="64" type="riscv_double"/>
+ <reg name="ft1" bitsize="64" type="riscv_double"/>
+ <reg name="ft2" bitsize="64" type="riscv_double"/>
+ <reg name="ft3" bitsize="64" type="riscv_double"/>
+ <reg name="ft4" bitsize="64" type="riscv_double"/>
+ <reg name="ft5" bitsize="64" type="riscv_double"/>
+ <reg name="ft6" bitsize="64" type="riscv_double"/>
+ <reg name="ft7" bitsize="64" type="riscv_double"/>
+ <reg name="fs0" bitsize="64" type="riscv_double"/>
+ <reg name="fs1" bitsize="64" type="riscv_double"/>
+ <reg name="fa0" bitsize="64" type="riscv_double"/>
+ <reg name="fa1" bitsize="64" type="riscv_double"/>
+ <reg name="fa2" bitsize="64" type="riscv_double"/>
+ <reg name="fa3" bitsize="64" type="riscv_double"/>
+ <reg name="fa4" bitsize="64" type="riscv_double"/>
+ <reg name="fa5" bitsize="64" type="riscv_double"/>
+ <reg name="fa6" bitsize="64" type="riscv_double"/>
+ <reg name="fa7" bitsize="64" type="riscv_double"/>
+ <reg name="fs2" bitsize="64" type="riscv_double"/>
+ <reg name="fs3" bitsize="64" type="riscv_double"/>
+ <reg name="fs4" bitsize="64" type="riscv_double"/>
+ <reg name="fs5" bitsize="64" type="riscv_double"/>
+ <reg name="fs6" bitsize="64" type="riscv_double"/>
+ <reg name="fs7" bitsize="64" type="riscv_double"/>
+ <reg name="fs8" bitsize="64" type="riscv_double"/>
+ <reg name="fs9" bitsize="64" type="riscv_double"/>
+ <reg name="fs10" bitsize="64" type="riscv_double"/>
+ <reg name="fs11" bitsize="64" type="riscv_double"/>
+ <reg name="ft8" bitsize="64" type="riscv_double"/>
+ <reg name="ft9" bitsize="64" type="riscv_double"/>
+ <reg name="ft10" bitsize="64" type="riscv_double"/>
+ <reg name="ft11" bitsize="64" type="riscv_double"/>
+
+ <reg name="fflags" bitsize="32" type="int"/>
+ <reg name="frm" bitsize="32" type="int"/>
+ <reg name="fcsr" bitsize="32" type="int"/>
+</feature>
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros.
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-02-12 23:07 ` [Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files Jim Wilson
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 2/5] RISC-V: Add 64-bit " Jim Wilson
@ 2019-02-12 23:08 ` Jim Wilson
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs Jim Wilson
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files Jim Wilson
4 siblings, 0 replies; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:08 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 35 +++++++++++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f47..316d500 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -135,16 +135,22 @@
/* Legacy Counter Setup (priv v1.9.1) */
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
+#define CSR_MHCOUNTEREN 0x322
/* Machine Trap Handling */
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+/* Legacy Machine Trap Handling (priv v1.9.1) */
+#define CSR_MBADADDR 0x343
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
@@ -153,9 +159,12 @@
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
+#define CSR_STVAL 0x143
#define CSR_SIP 0x144
+/* Legacy Supervisor Trap Handling (priv v1.9.1) */
+#define CSR_SBADADDR 0x143
+
/* Supervisor Protection and Translation */
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
@@ -282,6 +291,28 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
+#define CSR_HSTATUS 0x200
+#define CSR_HEDELEG 0x202
+#define CSR_HIDELEG 0x203
+#define CSR_HIE 0x204
+#define CSR_HTVEC 0x205
+
+/* Legacy Hypervisor Trap Handling (priv v1.9.1) */
+#define CSR_HSCRATCH 0x240
+#define CSR_HEPC 0x241
+#define CSR_HCAUSE 0x242
+#define CSR_HBADADDR 0x243
+#define CSR_HIP 0x244
+
+/* Legacy Machine Protection and Translation (priv v1.9.1) */
+#define CSR_MBASE 0x380
+#define CSR_MBOUND 0x381
+#define CSR_MIBASE 0x382
+#define CSR_MIBOUND 0x383
+#define CSR_MDBASE 0x384
+#define CSR_MDBOUND 0x385
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs.
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
` (2 preceding siblings ...)
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros Jim Wilson
@ 2019-02-12 23:09 ` Jim Wilson
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files Jim Wilson
4 siblings, 0 replies; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/csr.c | 34 ++++++++++++++++++++++++++--------
2 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743f02c..04a050e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -170,6 +170,9 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+
+ /* True if in debugger mode. */
+ bool debugger;
#endif
float_status fp_status;
@@ -292,6 +295,8 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
+int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask);
static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
int csrno)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d1..de28a5d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -58,7 +58,7 @@ static int ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
target_ulong ctr_en = env->priv == PRV_U ? env->scounteren :
env->priv == PRV_S ? env->mcounteren : -1U;
- if (!(ctr_en & (1 << (csrno & 31)))) {
+ if (!env->debugger && !(ctr_en & (1 << (csrno & 31)))) {
return -1;
}
#endif
@@ -86,7 +86,7 @@ static int pmp(CPURISCVState *env, int csrno)
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -97,7 +97,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -109,7 +109,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -120,7 +120,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -132,7 +132,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
#endif
@@ -144,7 +144,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- if (!(env->mstatus & MSTATUS_FS)) {
+ if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
}
env->mstatus |= MSTATUS_FS;
@@ -772,6 +772,24 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
return 0;
}
+/*
+ * Debugger support. If not in user mode, set env->debugger before the
+ * riscv_csrrw call and clear it after the call.
+ */
+int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret;
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = true;
+#endif
+ ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = false;
+#endif
+ return ret;
+}
+
/* Control and Status Register function table */
static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files.
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
` (3 preceding siblings ...)
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs Jim Wilson
@ 2019-02-12 23:09 ` Jim Wilson
2019-02-12 23:24 ` Alistair Francis
4 siblings, 1 reply; 7+ messages in thread
From: Jim Wilson @ 2019-02-12 23:09 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, Jim Wilson
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
fairly standard gdb hooks to access xml specified registers.
Signed-off-by: Jim Wilson <jimw@sifive.com>
---
target/riscv/cpu.c | 9 +-
target/riscv/cpu.h | 2 +
target/riscv/gdbstub.c | 348 +++++++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 347 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 28d7e53..c23bd01 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -311,6 +311,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
+ riscv_cpu_register_gdb_regs_for_features(cs);
+
qemu_init_vcpu(cs);
cpu_reset(cs);
@@ -351,7 +353,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
- cc->gdb_num_core_regs = 65;
+ cc->gdb_num_core_regs = 33;
+#if defined(TARGET_RISCV32)
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+#elif defined(TARGET_RISCV64)
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 04a050e..c10e86c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,8 @@ typedef struct {
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
+
#include "exec/cpu-all.h"
#endif /* RISCV_CPU_H */
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 3cabb21..621206d 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -21,6 +21,255 @@
#include "exec/gdbstub.h"
#include "cpu.h"
+/*
+ * The GDB CSR xml files list them in documentation order, not numerical order,
+ * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
+ * to the hardware numbers.
+ */
+
+static int csr_register_map[] = {
+ CSR_USTATUS,
+ CSR_UIE,
+ CSR_UTVEC,
+ CSR_USCRATCH,
+ CSR_UEPC,
+ CSR_UCAUSE,
+ CSR_UTVAL,
+ CSR_UIP,
+ CSR_FFLAGS,
+ CSR_FRM,
+ CSR_FCSR,
+ CSR_CYCLE,
+ CSR_TIME,
+ CSR_INSTRET,
+ CSR_HPMCOUNTER3,
+ CSR_HPMCOUNTER4,
+ CSR_HPMCOUNTER5,
+ CSR_HPMCOUNTER6,
+ CSR_HPMCOUNTER7,
+ CSR_HPMCOUNTER8,
+ CSR_HPMCOUNTER9,
+ CSR_HPMCOUNTER10,
+ CSR_HPMCOUNTER11,
+ CSR_HPMCOUNTER12,
+ CSR_HPMCOUNTER13,
+ CSR_HPMCOUNTER14,
+ CSR_HPMCOUNTER15,
+ CSR_HPMCOUNTER16,
+ CSR_HPMCOUNTER17,
+ CSR_HPMCOUNTER18,
+ CSR_HPMCOUNTER19,
+ CSR_HPMCOUNTER20,
+ CSR_HPMCOUNTER21,
+ CSR_HPMCOUNTER22,
+ CSR_HPMCOUNTER23,
+ CSR_HPMCOUNTER24,
+ CSR_HPMCOUNTER25,
+ CSR_HPMCOUNTER26,
+ CSR_HPMCOUNTER27,
+ CSR_HPMCOUNTER28,
+ CSR_HPMCOUNTER29,
+ CSR_HPMCOUNTER30,
+ CSR_HPMCOUNTER31,
+ CSR_CYCLEH,
+ CSR_TIMEH,
+ CSR_INSTRETH,
+ CSR_HPMCOUNTER3H,
+ CSR_HPMCOUNTER4H,
+ CSR_HPMCOUNTER5H,
+ CSR_HPMCOUNTER6H,
+ CSR_HPMCOUNTER7H,
+ CSR_HPMCOUNTER8H,
+ CSR_HPMCOUNTER9H,
+ CSR_HPMCOUNTER10H,
+ CSR_HPMCOUNTER11H,
+ CSR_HPMCOUNTER12H,
+ CSR_HPMCOUNTER13H,
+ CSR_HPMCOUNTER14H,
+ CSR_HPMCOUNTER15H,
+ CSR_HPMCOUNTER16H,
+ CSR_HPMCOUNTER17H,
+ CSR_HPMCOUNTER18H,
+ CSR_HPMCOUNTER19H,
+ CSR_HPMCOUNTER20H,
+ CSR_HPMCOUNTER21H,
+ CSR_HPMCOUNTER22H,
+ CSR_HPMCOUNTER23H,
+ CSR_HPMCOUNTER24H,
+ CSR_HPMCOUNTER25H,
+ CSR_HPMCOUNTER26H,
+ CSR_HPMCOUNTER27H,
+ CSR_HPMCOUNTER28H,
+ CSR_HPMCOUNTER29H,
+ CSR_HPMCOUNTER30H,
+ CSR_HPMCOUNTER31H,
+ CSR_SSTATUS,
+ CSR_SEDELEG,
+ CSR_SIDELEG,
+ CSR_SIE,
+ CSR_STVEC,
+ CSR_SCOUNTEREN,
+ CSR_SSCRATCH,
+ CSR_SEPC,
+ CSR_SCAUSE,
+ CSR_STVAL,
+ CSR_SIP,
+ CSR_SATP,
+ CSR_MVENDORID,
+ CSR_MARCHID,
+ CSR_MIMPID,
+ CSR_MHARTID,
+ CSR_MSTATUS,
+ CSR_MISA,
+ CSR_MEDELEG,
+ CSR_MIDELEG,
+ CSR_MIE,
+ CSR_MTVEC,
+ CSR_MCOUNTEREN,
+ CSR_MSCRATCH,
+ CSR_MEPC,
+ CSR_MCAUSE,
+ CSR_MTVAL,
+ CSR_MIP,
+ CSR_PMPCFG0,
+ CSR_PMPCFG1,
+ CSR_PMPCFG2,
+ CSR_PMPCFG3,
+ CSR_PMPADDR0,
+ CSR_PMPADDR1,
+ CSR_PMPADDR2,
+ CSR_PMPADDR3,
+ CSR_PMPADDR4,
+ CSR_PMPADDR5,
+ CSR_PMPADDR6,
+ CSR_PMPADDR7,
+ CSR_PMPADDR8,
+ CSR_PMPADDR9,
+ CSR_PMPADDR10,
+ CSR_PMPADDR11,
+ CSR_PMPADDR12,
+ CSR_PMPADDR13,
+ CSR_PMPADDR14,
+ CSR_PMPADDR15,
+ CSR_MCYCLE,
+ CSR_MINSTRET,
+ CSR_MHPMCOUNTER3,
+ CSR_MHPMCOUNTER4,
+ CSR_MHPMCOUNTER5,
+ CSR_MHPMCOUNTER6,
+ CSR_MHPMCOUNTER7,
+ CSR_MHPMCOUNTER8,
+ CSR_MHPMCOUNTER9,
+ CSR_MHPMCOUNTER10,
+ CSR_MHPMCOUNTER11,
+ CSR_MHPMCOUNTER12,
+ CSR_MHPMCOUNTER13,
+ CSR_MHPMCOUNTER14,
+ CSR_MHPMCOUNTER15,
+ CSR_MHPMCOUNTER16,
+ CSR_MHPMCOUNTER17,
+ CSR_MHPMCOUNTER18,
+ CSR_MHPMCOUNTER19,
+ CSR_MHPMCOUNTER20,
+ CSR_MHPMCOUNTER21,
+ CSR_MHPMCOUNTER22,
+ CSR_MHPMCOUNTER23,
+ CSR_MHPMCOUNTER24,
+ CSR_MHPMCOUNTER25,
+ CSR_MHPMCOUNTER26,
+ CSR_MHPMCOUNTER27,
+ CSR_MHPMCOUNTER28,
+ CSR_MHPMCOUNTER29,
+ CSR_MHPMCOUNTER30,
+ CSR_MHPMCOUNTER31,
+ CSR_MCYCLEH,
+ CSR_MINSTRETH,
+ CSR_MHPMCOUNTER3H,
+ CSR_MHPMCOUNTER4H,
+ CSR_MHPMCOUNTER5H,
+ CSR_MHPMCOUNTER6H,
+ CSR_MHPMCOUNTER7H,
+ CSR_MHPMCOUNTER8H,
+ CSR_MHPMCOUNTER9H,
+ CSR_MHPMCOUNTER10H,
+ CSR_MHPMCOUNTER11H,
+ CSR_MHPMCOUNTER12H,
+ CSR_MHPMCOUNTER13H,
+ CSR_MHPMCOUNTER14H,
+ CSR_MHPMCOUNTER15H,
+ CSR_MHPMCOUNTER16H,
+ CSR_MHPMCOUNTER17H,
+ CSR_MHPMCOUNTER18H,
+ CSR_MHPMCOUNTER19H,
+ CSR_MHPMCOUNTER20H,
+ CSR_MHPMCOUNTER21H,
+ CSR_MHPMCOUNTER22H,
+ CSR_MHPMCOUNTER23H,
+ CSR_MHPMCOUNTER24H,
+ CSR_MHPMCOUNTER25H,
+ CSR_MHPMCOUNTER26H,
+ CSR_MHPMCOUNTER27H,
+ CSR_MHPMCOUNTER28H,
+ CSR_MHPMCOUNTER29H,
+ CSR_MHPMCOUNTER30H,
+ CSR_MHPMCOUNTER31H,
+ CSR_MHPMEVENT3,
+ CSR_MHPMEVENT4,
+ CSR_MHPMEVENT5,
+ CSR_MHPMEVENT6,
+ CSR_MHPMEVENT7,
+ CSR_MHPMEVENT8,
+ CSR_MHPMEVENT9,
+ CSR_MHPMEVENT10,
+ CSR_MHPMEVENT11,
+ CSR_MHPMEVENT12,
+ CSR_MHPMEVENT13,
+ CSR_MHPMEVENT14,
+ CSR_MHPMEVENT15,
+ CSR_MHPMEVENT16,
+ CSR_MHPMEVENT17,
+ CSR_MHPMEVENT18,
+ CSR_MHPMEVENT19,
+ CSR_MHPMEVENT20,
+ CSR_MHPMEVENT21,
+ CSR_MHPMEVENT22,
+ CSR_MHPMEVENT23,
+ CSR_MHPMEVENT24,
+ CSR_MHPMEVENT25,
+ CSR_MHPMEVENT26,
+ CSR_MHPMEVENT27,
+ CSR_MHPMEVENT28,
+ CSR_MHPMEVENT29,
+ CSR_MHPMEVENT30,
+ CSR_MHPMEVENT31,
+ CSR_TSELECT,
+ CSR_TDATA1,
+ CSR_TDATA2,
+ CSR_TDATA3,
+ CSR_DCSR,
+ CSR_DPC,
+ CSR_DSCRATCH,
+ CSR_HSTATUS,
+ CSR_HEDELEG,
+ CSR_HIDELEG,
+ CSR_HIE,
+ CSR_HTVEC,
+ CSR_HSCRATCH,
+ CSR_HEPC,
+ CSR_HCAUSE,
+ CSR_HBADADDR,
+ CSR_HIP,
+ CSR_MBASE,
+ CSR_MBOUND,
+ CSR_MIBASE,
+ CSR_MIBOUND,
+ CSR_MDBASE,
+ CSR_MDBOUND,
+ CSR_MUCOUNTEREN,
+ CSR_MSCOUNTEREN,
+ CSR_MHCOUNTEREN,
+};
+
int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -30,13 +279,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]);
} else if (n == 32) {
return gdb_get_regl(mem_buf, env->pc);
- } else if (n < 65) {
- return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
- } else if (n < 4096 + 65) {
- target_ulong val = 0;
- if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) {
- return gdb_get_regl(mem_buf, val);
- }
}
return 0;
}
@@ -55,14 +297,98 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else if (n == 32) {
env->pc = ldtul_p(mem_buf);
return sizeof(target_ulong);
- } else if (n < 65) {
- env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
+ }
+ return 0;
+}
+
+static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ return gdb_get_reg64(mem_buf, env->fpr[n]);
+ } else if (n < 35) {
+ target_ulong val = 0;
+ int result;
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ result = riscv_csrrw_debug(env, n - 31, &val, 0, 0);
+ if (result == 0) {
+ return gdb_get_regl(mem_buf, val);
+ }
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < 32) {
+ env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
return sizeof(uint64_t);
- } else if (n < 4096 + 65) {
+ } else if (n < 35) {
target_ulong val = ldtul_p(mem_buf);
- if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) {
+ int result;
+ /*
+ * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
+ * subtract 31 to map the gdb FP register number to the CSR number.
+ * This also works for CSR_FRM and CSR_FCSR.
+ */
+ result = riscv_csrrw_debug(env, n - 31, NULL, val, -1);
+ if (result == 0) {
return sizeof(target_ulong);
}
}
return 0;
}
+
+static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ target_ulong val = 0;
+ int result;
+
+ result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
+ if (result == 0) {
+ return gdb_get_regl(mem_buf, val);
+ }
+ }
+ return 0;
+}
+
+static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ if (n < ARRAY_SIZE(csr_register_map)) {
+ target_ulong val = ldtul_p(mem_buf);
+ int result;
+
+ result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
+ if (result == 0) {
+ return sizeof(target_ulong);
+ }
+ }
+ return 0;
+}
+
+void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+#if defined(TARGET_RISCV32)
+ if (env->misa & RVF) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-32bit-fpu.xml", 0);
+ }
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-32bit-csr.xml", 0);
+#elif defined(TARGET_RISCV64)
+ if (env->misa & RVF) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
+ 35, "riscv-64bit-fpu.xml", 0);
+ }
+
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ 4096, "riscv-64bit-csr.xml", 0);
+#endif
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files.
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files Jim Wilson
@ 2019-02-12 23:24 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2019-02-12 23:24 UTC (permalink / raw)
To: Jim Wilson; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Tue, Feb 12, 2019 at 3:10 PM Jim Wilson <jimw@sifive.com> wrote:
>
> The gdb CSR xml file has registers in documentation order, not numerical
> order, so we need a table to map the register numbers. This also adds
> fairly standard gdb hooks to access xml specified registers.
>
> Signed-off-by: Jim Wilson <jimw@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 9 +-
> target/riscv/cpu.h | 2 +
> target/riscv/gdbstub.c | 348 +++++++++++++++++++++++++++++++++++++++++++++++--
> 3 files changed, 347 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 28d7e53..c23bd01 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -311,6 +311,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> + riscv_cpu_register_gdb_regs_for_features(cs);
> +
> qemu_init_vcpu(cs);
> cpu_reset(cs);
>
> @@ -351,7 +353,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
> cc->gdb_read_register = riscv_cpu_gdb_read_register;
> cc->gdb_write_register = riscv_cpu_gdb_write_register;
> - cc->gdb_num_core_regs = 65;
> + cc->gdb_num_core_regs = 33;
> +#if defined(TARGET_RISCV32)
> + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
> +#elif defined(TARGET_RISCV64)
> + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
> +#endif
> cc->gdb_stop_before_watchpoint = true;
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifdef CONFIG_USER_ONLY
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 04a050e..c10e86c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -329,6 +329,8 @@ typedef struct {
> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
> void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> +
> #include "exec/cpu-all.h"
>
> #endif /* RISCV_CPU_H */
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 3cabb21..621206d 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -21,6 +21,255 @@
> #include "exec/gdbstub.h"
> #include "cpu.h"
>
> +/*
> + * The GDB CSR xml files list them in documentation order, not numerical order,
> + * and are missing entries for unnamed CSRs. So we need to map the gdb numbers
> + * to the hardware numbers.
> + */
> +
> +static int csr_register_map[] = {
> + CSR_USTATUS,
> + CSR_UIE,
> + CSR_UTVEC,
> + CSR_USCRATCH,
> + CSR_UEPC,
> + CSR_UCAUSE,
> + CSR_UTVAL,
> + CSR_UIP,
> + CSR_FFLAGS,
> + CSR_FRM,
> + CSR_FCSR,
> + CSR_CYCLE,
> + CSR_TIME,
> + CSR_INSTRET,
> + CSR_HPMCOUNTER3,
> + CSR_HPMCOUNTER4,
> + CSR_HPMCOUNTER5,
> + CSR_HPMCOUNTER6,
> + CSR_HPMCOUNTER7,
> + CSR_HPMCOUNTER8,
> + CSR_HPMCOUNTER9,
> + CSR_HPMCOUNTER10,
> + CSR_HPMCOUNTER11,
> + CSR_HPMCOUNTER12,
> + CSR_HPMCOUNTER13,
> + CSR_HPMCOUNTER14,
> + CSR_HPMCOUNTER15,
> + CSR_HPMCOUNTER16,
> + CSR_HPMCOUNTER17,
> + CSR_HPMCOUNTER18,
> + CSR_HPMCOUNTER19,
> + CSR_HPMCOUNTER20,
> + CSR_HPMCOUNTER21,
> + CSR_HPMCOUNTER22,
> + CSR_HPMCOUNTER23,
> + CSR_HPMCOUNTER24,
> + CSR_HPMCOUNTER25,
> + CSR_HPMCOUNTER26,
> + CSR_HPMCOUNTER27,
> + CSR_HPMCOUNTER28,
> + CSR_HPMCOUNTER29,
> + CSR_HPMCOUNTER30,
> + CSR_HPMCOUNTER31,
> + CSR_CYCLEH,
> + CSR_TIMEH,
> + CSR_INSTRETH,
> + CSR_HPMCOUNTER3H,
> + CSR_HPMCOUNTER4H,
> + CSR_HPMCOUNTER5H,
> + CSR_HPMCOUNTER6H,
> + CSR_HPMCOUNTER7H,
> + CSR_HPMCOUNTER8H,
> + CSR_HPMCOUNTER9H,
> + CSR_HPMCOUNTER10H,
> + CSR_HPMCOUNTER11H,
> + CSR_HPMCOUNTER12H,
> + CSR_HPMCOUNTER13H,
> + CSR_HPMCOUNTER14H,
> + CSR_HPMCOUNTER15H,
> + CSR_HPMCOUNTER16H,
> + CSR_HPMCOUNTER17H,
> + CSR_HPMCOUNTER18H,
> + CSR_HPMCOUNTER19H,
> + CSR_HPMCOUNTER20H,
> + CSR_HPMCOUNTER21H,
> + CSR_HPMCOUNTER22H,
> + CSR_HPMCOUNTER23H,
> + CSR_HPMCOUNTER24H,
> + CSR_HPMCOUNTER25H,
> + CSR_HPMCOUNTER26H,
> + CSR_HPMCOUNTER27H,
> + CSR_HPMCOUNTER28H,
> + CSR_HPMCOUNTER29H,
> + CSR_HPMCOUNTER30H,
> + CSR_HPMCOUNTER31H,
> + CSR_SSTATUS,
> + CSR_SEDELEG,
> + CSR_SIDELEG,
> + CSR_SIE,
> + CSR_STVEC,
> + CSR_SCOUNTEREN,
> + CSR_SSCRATCH,
> + CSR_SEPC,
> + CSR_SCAUSE,
> + CSR_STVAL,
> + CSR_SIP,
> + CSR_SATP,
> + CSR_MVENDORID,
> + CSR_MARCHID,
> + CSR_MIMPID,
> + CSR_MHARTID,
> + CSR_MSTATUS,
> + CSR_MISA,
> + CSR_MEDELEG,
> + CSR_MIDELEG,
> + CSR_MIE,
> + CSR_MTVEC,
> + CSR_MCOUNTEREN,
> + CSR_MSCRATCH,
> + CSR_MEPC,
> + CSR_MCAUSE,
> + CSR_MTVAL,
> + CSR_MIP,
> + CSR_PMPCFG0,
> + CSR_PMPCFG1,
> + CSR_PMPCFG2,
> + CSR_PMPCFG3,
> + CSR_PMPADDR0,
> + CSR_PMPADDR1,
> + CSR_PMPADDR2,
> + CSR_PMPADDR3,
> + CSR_PMPADDR4,
> + CSR_PMPADDR5,
> + CSR_PMPADDR6,
> + CSR_PMPADDR7,
> + CSR_PMPADDR8,
> + CSR_PMPADDR9,
> + CSR_PMPADDR10,
> + CSR_PMPADDR11,
> + CSR_PMPADDR12,
> + CSR_PMPADDR13,
> + CSR_PMPADDR14,
> + CSR_PMPADDR15,
> + CSR_MCYCLE,
> + CSR_MINSTRET,
> + CSR_MHPMCOUNTER3,
> + CSR_MHPMCOUNTER4,
> + CSR_MHPMCOUNTER5,
> + CSR_MHPMCOUNTER6,
> + CSR_MHPMCOUNTER7,
> + CSR_MHPMCOUNTER8,
> + CSR_MHPMCOUNTER9,
> + CSR_MHPMCOUNTER10,
> + CSR_MHPMCOUNTER11,
> + CSR_MHPMCOUNTER12,
> + CSR_MHPMCOUNTER13,
> + CSR_MHPMCOUNTER14,
> + CSR_MHPMCOUNTER15,
> + CSR_MHPMCOUNTER16,
> + CSR_MHPMCOUNTER17,
> + CSR_MHPMCOUNTER18,
> + CSR_MHPMCOUNTER19,
> + CSR_MHPMCOUNTER20,
> + CSR_MHPMCOUNTER21,
> + CSR_MHPMCOUNTER22,
> + CSR_MHPMCOUNTER23,
> + CSR_MHPMCOUNTER24,
> + CSR_MHPMCOUNTER25,
> + CSR_MHPMCOUNTER26,
> + CSR_MHPMCOUNTER27,
> + CSR_MHPMCOUNTER28,
> + CSR_MHPMCOUNTER29,
> + CSR_MHPMCOUNTER30,
> + CSR_MHPMCOUNTER31,
> + CSR_MCYCLEH,
> + CSR_MINSTRETH,
> + CSR_MHPMCOUNTER3H,
> + CSR_MHPMCOUNTER4H,
> + CSR_MHPMCOUNTER5H,
> + CSR_MHPMCOUNTER6H,
> + CSR_MHPMCOUNTER7H,
> + CSR_MHPMCOUNTER8H,
> + CSR_MHPMCOUNTER9H,
> + CSR_MHPMCOUNTER10H,
> + CSR_MHPMCOUNTER11H,
> + CSR_MHPMCOUNTER12H,
> + CSR_MHPMCOUNTER13H,
> + CSR_MHPMCOUNTER14H,
> + CSR_MHPMCOUNTER15H,
> + CSR_MHPMCOUNTER16H,
> + CSR_MHPMCOUNTER17H,
> + CSR_MHPMCOUNTER18H,
> + CSR_MHPMCOUNTER19H,
> + CSR_MHPMCOUNTER20H,
> + CSR_MHPMCOUNTER21H,
> + CSR_MHPMCOUNTER22H,
> + CSR_MHPMCOUNTER23H,
> + CSR_MHPMCOUNTER24H,
> + CSR_MHPMCOUNTER25H,
> + CSR_MHPMCOUNTER26H,
> + CSR_MHPMCOUNTER27H,
> + CSR_MHPMCOUNTER28H,
> + CSR_MHPMCOUNTER29H,
> + CSR_MHPMCOUNTER30H,
> + CSR_MHPMCOUNTER31H,
> + CSR_MHPMEVENT3,
> + CSR_MHPMEVENT4,
> + CSR_MHPMEVENT5,
> + CSR_MHPMEVENT6,
> + CSR_MHPMEVENT7,
> + CSR_MHPMEVENT8,
> + CSR_MHPMEVENT9,
> + CSR_MHPMEVENT10,
> + CSR_MHPMEVENT11,
> + CSR_MHPMEVENT12,
> + CSR_MHPMEVENT13,
> + CSR_MHPMEVENT14,
> + CSR_MHPMEVENT15,
> + CSR_MHPMEVENT16,
> + CSR_MHPMEVENT17,
> + CSR_MHPMEVENT18,
> + CSR_MHPMEVENT19,
> + CSR_MHPMEVENT20,
> + CSR_MHPMEVENT21,
> + CSR_MHPMEVENT22,
> + CSR_MHPMEVENT23,
> + CSR_MHPMEVENT24,
> + CSR_MHPMEVENT25,
> + CSR_MHPMEVENT26,
> + CSR_MHPMEVENT27,
> + CSR_MHPMEVENT28,
> + CSR_MHPMEVENT29,
> + CSR_MHPMEVENT30,
> + CSR_MHPMEVENT31,
> + CSR_TSELECT,
> + CSR_TDATA1,
> + CSR_TDATA2,
> + CSR_TDATA3,
> + CSR_DCSR,
> + CSR_DPC,
> + CSR_DSCRATCH,
> + CSR_HSTATUS,
> + CSR_HEDELEG,
> + CSR_HIDELEG,
> + CSR_HIE,
> + CSR_HTVEC,
> + CSR_HSCRATCH,
> + CSR_HEPC,
> + CSR_HCAUSE,
> + CSR_HBADADDR,
> + CSR_HIP,
> + CSR_MBASE,
> + CSR_MBOUND,
> + CSR_MIBASE,
> + CSR_MIBOUND,
> + CSR_MDBASE,
> + CSR_MDBOUND,
> + CSR_MUCOUNTEREN,
> + CSR_MSCOUNTEREN,
> + CSR_MHCOUNTEREN,
> +};
> +
> int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> @@ -30,13 +279,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> return gdb_get_regl(mem_buf, env->gpr[n]);
> } else if (n == 32) {
> return gdb_get_regl(mem_buf, env->pc);
> - } else if (n < 65) {
> - return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
> - } else if (n < 4096 + 65) {
> - target_ulong val = 0;
> - if (riscv_csrrw(env, n - 65, &val, 0, 0) == 0) {
> - return gdb_get_regl(mem_buf, val);
> - }
> }
> return 0;
> }
> @@ -55,14 +297,98 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> } else if (n == 32) {
> env->pc = ldtul_p(mem_buf);
> return sizeof(target_ulong);
> - } else if (n < 65) {
> - env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + return gdb_get_reg64(mem_buf, env->fpr[n]);
> + } else if (n < 35) {
> + target_ulong val = 0;
> + int result;
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + result = riscv_csrrw_debug(env, n - 31, &val, 0, 0);
> + if (result == 0) {
> + return gdb_get_regl(mem_buf, val);
> + }
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < 32) {
> + env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
> return sizeof(uint64_t);
> - } else if (n < 4096 + 65) {
> + } else if (n < 35) {
> target_ulong val = ldtul_p(mem_buf);
> - if (riscv_csrrw(env, n - 65, NULL, val, -1) == 0) {
> + int result;
> + /*
> + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we
> + * subtract 31 to map the gdb FP register number to the CSR number.
> + * This also works for CSR_FRM and CSR_FCSR.
> + */
> + result = riscv_csrrw_debug(env, n - 31, NULL, val, -1);
> + if (result == 0) {
> return sizeof(target_ulong);
> }
> }
> return 0;
> }
> +
> +static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + target_ulong val = 0;
> + int result;
> +
> + result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
> + if (result == 0) {
> + return gdb_get_regl(mem_buf, val);
> + }
> + }
> + return 0;
> +}
> +
> +static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
> +{
> + if (n < ARRAY_SIZE(csr_register_map)) {
> + target_ulong val = ldtul_p(mem_buf);
> + int result;
> +
> + result = riscv_csrrw_debug(env, csr_register_map[n], NULL, val, -1);
> + if (result == 0) {
> + return sizeof(target_ulong);
> + }
> + }
> + return 0;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +#if defined(TARGET_RISCV32)
> + if (env->misa & RVF) {
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-32bit-fpu.xml", 0);
> + }
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-32bit-csr.xml", 0);
> +#elif defined(TARGET_RISCV64)
> + if (env->misa & RVF) {
> + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> + 35, "riscv-64bit-fpu.xml", 0);
> + }
> +
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + 4096, "riscv-64bit-csr.xml", 0);
> +#endif
> +}
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-02-12 23:26 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-02-12 23:04 [Qemu-devel] [PATCH v4 0/5] RISC-V: Add gdb xml files and gdbstub support Jim Wilson
2019-02-12 23:07 ` [Qemu-devel] [PATCH v4 1/5] RISC-V: Add 32-bit gdb xml files Jim Wilson
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 2/5] RISC-V: Add 64-bit " Jim Wilson
2019-02-12 23:08 ` [Qemu-devel] [PATCH v4 3/5] RISC-V: Fixes to CSR_* register macros Jim Wilson
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 4/5] RISC-V: Add debug support for accessing CSRs Jim Wilson
2019-02-12 23:09 ` [Qemu-devel] [PATCH v4 5/5] RISC-V: Add hooks to use the gdb xml files Jim Wilson
2019-02-12 23:24 ` Alistair Francis
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