From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:59642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtwtL-0001ut-CM for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtwtJ-0002rk-Su for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:07 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37409) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gtwtH-0000rK-CF for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:05 -0500 Received: by mail-pf1-x441.google.com with SMTP id s22so1326992pfh.4 for ; Wed, 13 Feb 2019 07:54:39 -0800 (PST) Date: Wed, 13 Feb 2019 07:53:40 -0800 Message-Id: <20190213155414.22285-2-palmer@sifive.com> In-Reply-To: <20190213155414.22285-1-palmer@sifive.com> References: <20190213155414.22285-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Bastian Koppelmann From: Bastian Koppelmann CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Bastian Koppelmann --- target/riscv/translate.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b7176cbf98e1..9e06eb8c2de5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -54,6 +54,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + CPURISCVState *env; } DisasContext; /* convert riscv funct3 to qemu memop for load/store */ @@ -2003,7 +2004,7 @@ static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ if (extract32(ctx->opcode, 0, 2) != 3) { - if (!has_ext(ctx, RVC)) { + if (!riscv_has_ext(ctx->env, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; @@ -2058,9 +2059,9 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - CPURISCVState *env = cpu->env_ptr; + ctx->env = cpu->env_ptr; - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next = ctx->pc_succ_insn; -- 2.18.1