From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:59953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gtwtU-000250-Pg for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gtwtN-000301-8d for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:16 -0500 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:42011) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gtwtM-0001yY-Nf for qemu-devel@nongnu.org; Wed, 13 Feb 2019 10:56:08 -0500 Received: by mail-pg1-x542.google.com with SMTP id d72so1303931pga.9 for ; Wed, 13 Feb 2019 07:55:24 -0800 (PST) Date: Wed, 13 Feb 2019 07:54:08 -0800 Message-Id: <20190213155414.22285-30-palmer@sifive.com> In-Reply-To: <20190213155414.22285-1-palmer@sifive.com> References: <20190213155414.22285-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PATCH v7 29/35] target/riscv: Remove gen_system() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Bastian Koppelmann , Peer Adelt From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3d49c8ed4054..65bedc966497 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -474,33 +474,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } -static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1, - int csr) -{ - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - - switch (opc) { - case OPC_RISC_ECALL: - switch (csr) { - case 0x0: /* ECALL */ - /* always generates U-level ECALL, fixed in do_interrupt handler */ - generate_exception(ctx, RISCV_EXCP_U_ECALL); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - case 0x1: /* EBREAK */ - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); - tcg_gen_exit_tb(NULL, 0); /* no chaining */ - ctx->base.is_jmp = DISAS_NORETURN; - break; - default: - gen_exception_illegal(ctx); - break; - } - break; - } -} - static void decode_RV32_64C0(DisasContext *ctx) { uint8_t funct3 = extract32(ctx->opcode, 13, 3); @@ -675,7 +648,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn); static void decode_RV32_64G(DisasContext *ctx) { - int rs1, rd; uint32_t op; /* We do not do misaligned address check here: the address should never be @@ -684,14 +656,8 @@ static void decode_RV32_64G(DisasContext *ctx) * perform the misaligned instruction fetch */ op = MASK_OP_MAJOR(ctx->opcode); - rs1 = GET_RS1(ctx->opcode); - rd = GET_RD(ctx->opcode); switch (op) { - case OPC_RISC_SYSTEM: - gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, - (ctx->opcode & 0xFFF00000) >> 20); - break; default: gen_exception_illegal(ctx); break; -- 2.18.1