From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 06/10] target/ppc: Add POWER9 exception model
Date: Fri, 15 Feb 2019 17:16:44 +0100 [thread overview]
Message-ID: <20190215161648.9600-7-clg@kaod.org> (raw)
In-Reply-To: <20190215161648.9600-1-clg@kaod.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
And use it to get the correct HILE bit in HID0
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu-qom.h | 2 ++
target/ppc/excp_helper.c | 17 +++++++++++++----
target/ppc/translate.c | 3 ++-
target/ppc/translate_init.inc.c | 2 +-
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index e9cb15842387..904ee694ac40 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -113,6 +113,8 @@ enum powerpc_excp_t {
POWERPC_EXCP_POWER7,
/* POWER8 exception model */
POWERPC_EXCP_POWER8,
+ /* POWER9 exception model */
+ POWERPC_EXCP_POWER9,
};
/*****************************************************************************/
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7536620a4133..37546bb0f0fe 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -147,7 +147,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* Exception targetting modifiers
*
- * LPES0 is supported on POWER7/8
+ * LPES0 is supported on POWER7/8/9
* LPES1 is not supported (old iSeries mode)
*
* On anything else, we behave as if LPES0 is 1
@@ -158,9 +158,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
*/
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8) {
+ excp_model == POWERPC_EXCP_POWER8 ||
+ excp_model == POWERPC_EXCP_POWER9) {
lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- if (excp_model == POWERPC_EXCP_POWER8) {
+ if (excp_model != POWERPC_EXCP_POWER7) {
ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
} else {
ail = 0;
@@ -662,7 +663,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
} else if (excp_model == POWERPC_EXCP_POWER8) {
if (new_msr & MSR_HVB) {
- if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) {
+ if (env->spr[SPR_HID0] & HID0_HILE) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+ } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
+ new_msr |= (target_ulong)1 << MSR_LE;
+ }
+ } else if (excp_model == POWERPC_EXCP_POWER9) {
+ if (new_msr & MSR_HVB) {
+ if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
new_msr |= (target_ulong)1 << MSR_LE;
}
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 75d170d1594f..106c43695252 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7480,7 +7480,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
#if defined(TARGET_PPC64)
if (env->excp_model == POWERPC_EXCP_POWER7 ||
- env->excp_model == POWERPC_EXCP_POWER8) {
+ env->excp_model == POWERPC_EXCP_POWER8 ||
+ env->excp_model == POWERPC_EXCP_POWER9) {
cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
}
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 1cfb70aced12..f8a780e323f2 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8905,7 +8905,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->hash64_opts = &ppc_hash64_opts_POWER7;
pcc->radix_page_info = &POWER9_radix_page_info;
#endif
- pcc->excp_model = POWERPC_EXCP_POWER8;
+ pcc->excp_model = POWERPC_EXCP_POWER9;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
pcc->bfd_mach = bfd_mach_ppc64;
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
--
2.20.1
next prev parent reply other threads:[~2019-02-15 16:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-15 16:16 [Qemu-devel] [PATCH 00/10] ppc: Add Hypervisor Virtualization Interrupt on POWER9 Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 01/10] target/ppc: Fix nip on power management instructions Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 02/10] target/ppc: Don't clobber MSR:EE on PM instructions Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 03/10] target/ppc: Fix support for "STOP light" states on POWER9 Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 04/10] target/ppc: Move "wakeup reset" code to a separate function Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 05/10] target/ppc: Rename "in_pm_state" to "resume_as_sreset" Cédric Le Goater
2019-02-15 16:16 ` Cédric Le Goater [this message]
2019-02-15 16:16 ` [Qemu-devel] [PATCH 07/10] target/ppc: Detect erroneous condition in interrupt delivery Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 08/10] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9 Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 09/10] target/ppc: Add POWER9 external interrupt model Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 10/10] target/ppc: Add support for LPCR:HEIC on POWER9 Cédric Le Goater
2019-02-19 0:44 ` [Qemu-devel] [PATCH 00/10] ppc: Add Hypervisor Virtualization Interrupt " David Gibson
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