From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 08/10] target/ppc: Add Hypervisor Virtualization Interrupt on POWER9
Date: Fri, 15 Feb 2019 17:16:46 +0100 [thread overview]
Message-ID: <20190215161648.9600-9-clg@kaod.org> (raw)
In-Reply-To: <20190215161648.9600-1-clg@kaod.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This adds support for delivering that exception
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 5 ++++-
target/ppc/excp_helper.c | 17 ++++++++++++++++-
target/ppc/translate_init.inc.c | 16 +++++++++++++++-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 945cb4bb7dde..ce55aa209770 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -160,8 +160,10 @@ enum {
/* Server doorbell variants */
POWERPC_EXCP_SDOOR = 99,
POWERPC_EXCP_SDOOR_HV = 100,
+ /* ISA 3.00 additions */
+ POWERPC_EXCP_HVIRT = 101,
/* EOL */
- POWERPC_EXCP_NB = 101,
+ POWERPC_EXCP_NB = 102,
/* QEMU exceptions: used internally during code translation */
POWERPC_EXCP_STOP = 0x200, /* stop translation */
POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
@@ -2349,6 +2351,7 @@ enum {
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
+ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
};
/* Processor Compatibility mask (PCR) */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1a2f469a5fa2..d171a5eb6236 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -97,6 +97,9 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
case POWERPC_EXCP_HV_MAINT:
*msr |= 0xaull << (63 - 45);
break;
+ case POWERPC_EXCP_HVIRT:
+ *msr |= 0x9ull << (63 - 45);
+ break;
default:
cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
excp);
@@ -427,6 +430,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
case POWERPC_EXCP_HV_EMU:
+ case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
@@ -809,7 +813,18 @@ static void ppc_hw_interrupt(CPUPPCState *env)
return;
}
}
- /* Extermal interrupt can ignore MSR:EE under some circumstances */
+
+ /* Hypervisor virtualization interrupt */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
+ /* LPCR will be clear when not supported so this will work */
+ bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
+ if ((async_deliver || msr_hv == 0) && hvice) {
+ powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HVIRT);
+ return;
+ }
+ }
+
+ /* External interrupt can ignore MSR:EE under some circumstances */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
if (async_deliver || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index f8a780e323f2..ae88e004faef 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -3313,6 +3313,15 @@ static void init_excp_POWER8(CPUPPCState *env)
#endif
}
+static void init_excp_POWER9(CPUPPCState *env)
+{
+ init_excp_POWER8(env);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
+#endif
+}
+
#endif
/*****************************************************************************/
@@ -8783,7 +8792,7 @@ static void init_proc_POWER9(CPUPPCState *env)
env->icache_line_size = 128;
/* Allocate hardware IRQ controller */
- init_excp_POWER8(env);
+ init_excp_POWER9(env);
ppcPOWER7_irq_init(ppc_env_get_cpu(env));
}
@@ -8836,6 +8845,11 @@ static bool cpu_has_work_POWER9(CPUState *cs)
(env->spr[SPR_LPCR] & LPCR_HDEE)) {
return true;
}
+ /* Hypervisor virtualization exception */
+ if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
+ (env->spr[SPR_LPCR] & LPCR_HVEE)) {
+ return true;
+ }
if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
return true;
}
--
2.20.1
next prev parent reply other threads:[~2019-02-15 16:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-15 16:16 [Qemu-devel] [PATCH 00/10] ppc: Add Hypervisor Virtualization Interrupt on POWER9 Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 01/10] target/ppc: Fix nip on power management instructions Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 02/10] target/ppc: Don't clobber MSR:EE on PM instructions Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 03/10] target/ppc: Fix support for "STOP light" states on POWER9 Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 04/10] target/ppc: Move "wakeup reset" code to a separate function Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 05/10] target/ppc: Rename "in_pm_state" to "resume_as_sreset" Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 06/10] target/ppc: Add POWER9 exception model Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 07/10] target/ppc: Detect erroneous condition in interrupt delivery Cédric Le Goater
2019-02-15 16:16 ` Cédric Le Goater [this message]
2019-02-15 16:16 ` [Qemu-devel] [PATCH 09/10] target/ppc: Add POWER9 external interrupt model Cédric Le Goater
2019-02-15 16:16 ` [Qemu-devel] [PATCH 10/10] target/ppc: Add support for LPCR:HEIC on POWER9 Cédric Le Goater
2019-02-19 0:44 ` [Qemu-devel] [PATCH 00/10] ppc: Add Hypervisor Virtualization Interrupt " David Gibson
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