[Qemu-devel] [PATCH 0/2] target/hppa: Minor fix and improvement

[Qemu-devel] [PATCH 0/2] target/hppa: Minor fix and improvement

[Richard Henderson]

The first patch is via inspection.  Linux only uses priv
levels 0 and 3, and I suspect that HP-UX is the same.

The second patch comes from examining traces.


r~


Richard Henderson (2):
  target/hppa: Do not return freed temporary
  target/hppa: Optimize blr r0,rn

 target/hppa/translate.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH 1/2] target/hppa: Do not return freed temporary

[Richard Henderson]

For priv levels 1 & 2, we were doing so from do_ibranch_priv.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index b4fd307b77..dad8ce563c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2007,16 +2007,15 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
         /* Privilege 0 is maximum and is allowed to decrease.  */
         return offset;
     case 3:
-        /* Privilege 3 is minimum and is never allowed increase.  */
+        /* Privilege 3 is minimum and is never allowed to increase.  */
         dest = get_temp(ctx);
         tcg_gen_ori_reg(dest, offset, 3);
         break;
     default:
-        dest = tcg_temp_new();
+        dest = get_temp(ctx);
         tcg_gen_andi_reg(dest, offset, -4);
         tcg_gen_ori_reg(dest, dest, ctx->privilege);
         tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset);
-        tcg_temp_free(dest);
         break;
     }
     return dest;
-- 
2.17.2

Re: [Qemu-devel] [PATCH 1/2] target/hppa: Do not return freed temporary

[Philippe Mathieu-Daudé]

On 2/22/19 7:05 AM, Richard Henderson wrote:
> For priv levels 1 & 2, we were doing so from do_ibranch_priv.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/hppa/translate.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index b4fd307b77..dad8ce563c 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c
> @@ -2007,16 +2007,15 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
>          /* Privilege 0 is maximum and is allowed to decrease.  */
>          return offset;
>      case 3:
> -        /* Privilege 3 is minimum and is never allowed increase.  */
> +        /* Privilege 3 is minimum and is never allowed to increase.  */
>          dest = get_temp(ctx);
>          tcg_gen_ori_reg(dest, offset, 3);
>          break;
>      default:
> -        dest = tcg_temp_new();
> +        dest = get_temp(ctx);
>          tcg_gen_andi_reg(dest, offset, -4);
>          tcg_gen_ori_reg(dest, dest, ctx->privilege);
>          tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset);
> -        tcg_temp_free(dest);
>          break;
>      }
>      return dest;

Oops!

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

[Qemu-devel] [PATCH 2/2] target/hppa: Optimize blr r0,rn

[Richard Henderson]

We can eliminate an extra TB in this case, which merely
loads a "return address" into rn.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index dad8ce563c..dc5636fe94 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3488,12 +3488,16 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
 
 static bool trans_blr(DisasContext *ctx, arg_blr *a)
 {
-    TCGv_reg tmp = get_temp(ctx);
-
-    tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);
-    tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);
-    /* The computation here never changes privilege level.  */
-    return do_ibranch(ctx, tmp, a->l, a->n);
+    if (a->x) {
+        TCGv_reg tmp = get_temp(ctx);
+        tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);
+        tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);
+        /* The computation here never changes privilege level.  */
+        return do_ibranch(ctx, tmp, a->l, a->n);
+    } else {
+        /* BLR R0,RX is a good way to load PC+8 into RX.  */
+        return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n);
+    }
 }
 
 static bool trans_bv(DisasContext *ctx, arg_bv *a)
-- 
2.17.2