From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>
Subject: [Qemu-devel] [PATCH v8 14/34] target/riscv: Convert RV64D insns to decodetree
Date: Fri, 22 Feb 2019 15:10:04 +0100 [thread overview]
Message-ID: <20190222141024.22217-15-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
v7 -> v8:
- add missing RVD checks
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82 ++++
target/riscv/translate.c | 601 +-----------------------
3 files changed, 91 insertions(+), 600 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 6319f872ac..380bf791bc 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -62,3 +62,11 @@ fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
+
+# *** RV64D Standard Extension (in addition to RV32D) ***
+fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
+fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
+fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index 98fc1cdc5a..393fa0248c 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -358,3 +358,85 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
mark_fs_dirty(ctx);
return true;
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+ return true;
+}
+
+static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVD);
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+ tcg_temp_free(t0);
+ mark_fs_dirty(ctx);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c201985ef3..2e36deee82 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -186,44 +186,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_temp_free(rh);
}
-static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1,
- uint32_t rs2, int rm, uint64_t min)
-{
- switch (rm) {
- case 0: /* fsgnj */
- if (rs1 == rs2) { /* FMOV */
- tcg_gen_mov_i64(cpu_fpr[rd], cpu_fpr[rs1]);
- } else {
- tcg_gen_deposit_i64(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- }
- break;
- case 1: /* fsgnjn */
- if (rs1 == rs2) { /* FNEG */
- tcg_gen_xori_i64(cpu_fpr[rd], cpu_fpr[rs1], min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_not_i64(t0, cpu_fpr[rs2]);
- tcg_gen_deposit_i64(cpu_fpr[rd], t0, cpu_fpr[rs1],
- 0, min == INT32_MIN ? 31 : 63);
- tcg_temp_free_i64(t0);
- }
- break;
- case 2: /* fsgnjx */
- if (rs1 == rs2) { /* FABS */
- tcg_gen_andi_i64(cpu_fpr[rd], cpu_fpr[rs1], ~min);
- } else {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_andi_i64(t0, cpu_fpr[rs2], min);
- tcg_gen_xor_i64(cpu_fpr[rd], cpu_fpr[rs1], t0);
- tcg_temp_free_i64(t0);
- }
- break;
- default:
- gen_exception_illegal(ctx);
- }
-}
-
static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int rs2)
{
@@ -807,535 +769,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FMSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FMSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rs3, int rm)
-{
- switch (opc) {
- case OPC_RISC_FNMADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- case OPC_RISC_FNMADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
- cpu_fpr[rs2], cpu_fpr[rs3]);
- break;
- do_illegal:
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
-static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, int rs2, int rm)
-{
- TCGv t0 = NULL;
- bool fp_output = true;
-
- if (ctx->mstatus_fs == 0) {
- goto do_illegal;
- }
-
- switch (opc) {
- case OPC_RISC_FADD_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
- break;
-
- case OPC_RISC_FMIN_S:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- /* also handles: OPC_RISC_FMAX_S */
- switch (rm) {
- case 0x0:
- gen_helper_fmin_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_fmax_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_S:
- /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0x0:
- gen_helper_fle_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x1:
- gen_helper_flt_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 0x2:
- gen_helper_feq_s(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_W_S:
- /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0: /* FCVT_W_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1: /* FCVT_WU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_L_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3: /* FCVT_LU_S */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_S_W:
- /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0: /* FCVT_S_W */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1: /* FCVT_S_WU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2: /* FCVT_S_L */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3: /* FCVT_S_LU */
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_S:
- /* also OPC_RISC_FCLASS_S */
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0: /* FMV */
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(t0, cpu_fpr[rs1]);
-#else
- tcg_gen_extrl_i64_i32(t0, cpu_fpr[rs1]);
-#endif
- break;
- case 1:
- gen_helper_fclass_s(t0, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FMV_S_X:
- if (!has_ext(ctx, RVF)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[rd], t0);
-#endif
- tcg_temp_free(t0);
- break;
-
- /* double */
- case OPC_RISC_FADD_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSUB_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FMUL_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FDIV_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case OPC_RISC_FSQRT_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- gen_set_rm(ctx, rm);
- gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- case OPC_RISC_FSGNJ_D:
- gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN);
- break;
-
- case OPC_RISC_FMIN_D:
- /* also OPC_RISC_FMAX_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rm) {
- case 0:
- gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_fmax_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_S_D:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rs2) {
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_s_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FCVT_D_S:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
- break;
- default:
- goto do_illegal;
- }
- break;
-
- case OPC_RISC_FEQ_D:
- /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rm) {
- case 0:
- gen_helper_fle_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 1:
- gen_helper_flt_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- case 2:
- gen_helper_feq_d(t0, cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
- break;
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_W_D:
- /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[rs1]);
- break;
-#endif
- default:
- goto do_illegal;
- }
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- fp_output = false;
- break;
-
- case OPC_RISC_FCVT_D_W:
- /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- switch (rs2) {
- case 0:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_w(cpu_fpr[rd], cpu_env, t0);
- break;
- case 1:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_wu(cpu_fpr[rd], cpu_env, t0);
- break;
-#if defined(TARGET_RISCV64)
- case 2:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_l(cpu_fpr[rd], cpu_env, t0);
- break;
- case 3:
- gen_set_rm(ctx, rm);
- gen_helper_fcvt_d_lu(cpu_fpr[rd], cpu_env, t0);
- break;
-#endif
- default:
- goto do_illegal;
- }
- tcg_temp_free(t0);
- break;
-
- case OPC_RISC_FMV_X_D:
- /* also OPC_RISC_FCLASS_D */
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- switch (rm) {
-#if defined(TARGET_RISCV64)
- case 0: /* FMV */
- gen_set_gpr(rd, cpu_fpr[rs1]);
- break;
-#endif
- case 1:
- t0 = tcg_temp_new();
- gen_helper_fclass_d(t0, cpu_fpr[rs1]);
- gen_set_gpr(rd, t0);
- tcg_temp_free(t0);
- break;
- default:
- goto do_illegal;
- }
- fp_output = false;
- break;
-
-#if defined(TARGET_RISCV64)
- case OPC_RISC_FMV_D_X:
- if (!has_ext(ctx, RVD)) {
- goto do_illegal;
- }
- t0 = tcg_temp_new();
- gen_get_gpr(t0, rs1);
- tcg_gen_mov_tl(cpu_fpr[rd], t0);
- tcg_temp_free(t0);
- break;
-#endif
-
- default:
- do_illegal:
- if (t0) {
- tcg_temp_free(t0);
- }
- gen_exception_illegal(ctx);
- return;
- }
-
- if (fp_output) {
- mark_fs_dirty(ctx);
- }
-}
-
static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
int csr)
{
@@ -1722,11 +1155,8 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
static void decode_RV32_64G(DisasContext *ctx)
{
- int rs1;
- int rs2;
- int rd;
+ int rs1, rd;
uint32_t op;
- target_long imm;
/* We do not do misaligned address check here: the address should never be
* misaligned at this point. Instructions that set PC must do the check,
@@ -1735,38 +1165,9 @@ static void decode_RV32_64G(DisasContext *ctx)
op = MASK_OP_MAJOR(ctx->opcode);
rs1 = GET_RS1(ctx->opcode);
- rs2 = GET_RS2(ctx->opcode);
rd = GET_RD(ctx->opcode);
- imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_FP_LOAD:
- gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
- break;
- case OPC_RISC_FP_STORE:
- gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
- GET_STORE_IMM(ctx->opcode));
- break;
- case OPC_RISC_FMADD:
- gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FMSUB:
- gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMSUB:
- gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FNMADD:
- gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2,
- GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
- break;
- case OPC_RISC_FP_ARITH:
- gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
- GET_RM(ctx->opcode));
- break;
case OPC_RISC_SYSTEM:
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.20.1
next prev parent reply other threads:[~2019-02-22 14:12 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 14:09 [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 03/34] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 04/34] target/riscv: Convert RV64I " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 06/34] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 07/34] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 08/34] target/riscv: Convert RVXM " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 09/34] target/riscv: Convert RV32A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 10/34] target/riscv: Convert RV64A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 11/34] target/riscv: Convert RV32F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 12/34] target/riscv: Convert RV64F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 13/34] target/riscv: Convert RV32D " Bastian Koppelmann
2019-02-22 14:10 ` Bastian Koppelmann [this message]
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 15/34] target/riscv: Convert RV priv " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 17/34] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 18/34] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 19/34] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 28/34] target/riscv: Remove gen_system() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-02-22 23:16 ` [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Alistair Francis
2019-02-27 17:55 ` no-reply
2019-02-28 8:37 ` Thomas Huth
2019-02-28 9:06 ` Paolo Bonzini
2019-02-27 18:19 ` no-reply
2019-02-27 18:36 ` no-reply
2019-02-27 18:41 ` no-reply
2019-02-27 18:53 ` no-reply
2019-02-27 18:57 ` no-reply
2019-02-27 19:03 ` no-reply
2019-02-27 19:08 ` no-reply
2019-02-27 19:14 ` no-reply
2019-02-27 19:19 ` no-reply
2019-02-27 19:25 ` no-reply
2019-02-27 19:29 ` no-reply
2019-02-27 19:52 ` no-reply
2019-02-27 19:57 ` no-reply
2019-02-27 20:17 ` no-reply
2019-02-27 20:23 ` no-reply
2019-02-27 20:27 ` no-reply
2019-02-27 20:33 ` no-reply
2019-02-27 20:38 ` no-reply
2019-02-27 20:43 ` no-reply
2019-02-27 20:47 ` no-reply
2019-02-27 20:52 ` no-reply
2019-02-27 20:56 ` no-reply
2019-02-27 21:01 ` no-reply
2019-02-27 21:06 ` no-reply
2019-02-27 21:10 ` no-reply
2019-02-27 21:21 ` no-reply
2019-02-27 21:27 ` no-reply
2019-02-27 21:33 ` no-reply
2019-02-27 21:39 ` no-reply
2019-02-27 21:43 ` no-reply
2019-02-27 21:48 ` no-reply
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