From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions
Date: Fri, 22 Feb 2019 15:10:13 +0100 [thread overview]
Message-ID: <20190222141024.22217-24-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 98 +++++++++++++++++-----
target/riscv/translate.c | 107 ++++++------------------
3 files changed, 108 insertions(+), 100 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ecc46a50cc..d6b4197841 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,12 +35,13 @@
# Argument sets:
&b imm rs2 rs1
+&i imm rs1 rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
-@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 5a09c6335a..0265740bdb 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -217,52 +217,96 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shli_tl(t, t, a->shamt);
+
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_shri_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, a->rd, a->rs1, a->shamt | 0x400);
+ if (a->shamt >= TARGET_LONG_BITS) {
+ return false;
+ }
+
+ if (a->rd != 0) {
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+
+ tcg_gen_sari_tl(t, t, a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
+ } /* NOP otherwise */
return true;
}
@@ -329,26 +373,42 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
- return true;
+ return gen_arith_imm(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
return true;
}
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW, a->rd, a->rs1, a->shamt);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
+ /* sign-extend for W instructions */
+ tcg_gen_ext32s_tl(t, t);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
- gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
- a->shamt | 0x400);
+ TCGv t = tcg_temp_new();
+ gen_get_gpr(t, a->rs1);
+ tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
+ gen_set_gpr(a->rd, t);
+ tcg_temp_free(t);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cdc08b1bff..0157758a16 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -433,86 +433,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
-
- gen_get_gpr(source1, rs1);
-
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
-}
-
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@@ -785,6 +705,33 @@ static int ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
+
+static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_add_tl(ret, arg1, arg2);
+ tcg_gen_ext32s_tl(ret, ret);
+}
+#endif
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
next prev parent reply other threads:[~2019-02-22 14:13 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 14:09 [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 03/34] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 04/34] target/riscv: Convert RV64I " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 06/34] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 07/34] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 08/34] target/riscv: Convert RVXM " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 09/34] target/riscv: Convert RV32A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 10/34] target/riscv: Convert RV64A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 11/34] target/riscv: Convert RV32F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 12/34] target/riscv: Convert RV64F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 13/34] target/riscv: Convert RV32D " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 14/34] target/riscv: Convert RV64D " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 15/34] target/riscv: Convert RV priv " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 17/34] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 18/34] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 19/34] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-02-22 14:10 ` Bastian Koppelmann [this message]
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 28/34] target/riscv: Remove gen_system() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-02-22 23:16 ` [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Alistair Francis
2019-02-27 17:55 ` no-reply
2019-02-28 8:37 ` Thomas Huth
2019-02-28 9:06 ` Paolo Bonzini
2019-02-27 18:19 ` no-reply
2019-02-27 18:36 ` no-reply
2019-02-27 18:41 ` no-reply
2019-02-27 18:53 ` no-reply
2019-02-27 18:57 ` no-reply
2019-02-27 19:03 ` no-reply
2019-02-27 19:08 ` no-reply
2019-02-27 19:14 ` no-reply
2019-02-27 19:19 ` no-reply
2019-02-27 19:25 ` no-reply
2019-02-27 19:29 ` no-reply
2019-02-27 19:52 ` no-reply
2019-02-27 19:57 ` no-reply
2019-02-27 20:17 ` no-reply
2019-02-27 20:23 ` no-reply
2019-02-27 20:27 ` no-reply
2019-02-27 20:33 ` no-reply
2019-02-27 20:38 ` no-reply
2019-02-27 20:43 ` no-reply
2019-02-27 20:47 ` no-reply
2019-02-27 20:52 ` no-reply
2019-02-27 20:56 ` no-reply
2019-02-27 21:01 ` no-reply
2019-02-27 21:06 ` no-reply
2019-02-27 21:10 ` no-reply
2019-02-27 21:21 ` no-reply
2019-02-27 21:27 ` no-reply
2019-02-27 21:33 ` no-reply
2019-02-27 21:39 ` no-reply
2019-02-27 21:43 ` no-reply
2019-02-27 21:48 ` no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190222141024.22217-24-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=palmer@sifive.com \
--cc=peer.adelt@hni.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).