From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v8 25/34] target/riscv: Remove shift and slt insn manual decoding
Date: Fri, 22 Feb 2019 15:10:15 +0100 [thread overview]
Message-ID: <20190222141024.22217-26-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190222141024.22217-1-kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +++++++++++++++++--------
target/riscv/translate.c | 59 +++++-----------
2 files changed, 81 insertions(+), 71 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 8879f2da35..88ef0003ec 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -220,30 +220,25 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
}
-static bool trans_slti(DisasContext *ctx, arg_slti *a)
+static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
+ tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
+}
+
+static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+{
+ tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
+}
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+static bool trans_slti(DisasContext *ctx, arg_slti *a)
+{
+ return gen_arith_imm(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- TCGv source1;
- source1 = tcg_temp_new();
- gen_get_gpr(source1, a->rs1);
-
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
-
- gen_set_gpr(a->rd, source1);
- tcg_temp_free(source1);
- return true;
+ return gen_arith_imm(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -322,20 +317,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
- gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shl_tl);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -345,14 +337,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_shr_tl);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2);
- return true;
+ return gen_shift(ctx, a, &tcg_gen_sar_tl);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -419,19 +409,62 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
- gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shl_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
- gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /* clear upper 32 */
+ tcg_gen_ext32u_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_shr_tl(source1, source1, source2);
+
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
return true;
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
- gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2);
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ /*
+ * first, trick to get it to act like working on 32 bits (get rid of
+ * upper 32, sign extend to fill space)
+ */
+ tcg_gen_ext32s_tl(source1, source1);
+ tcg_gen_andi_tl(source2, source2, 0x1F);
+ tcg_gen_sar_tl(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8eb8834633..9ae40f6509 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -198,47 +198,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
gen_get_gpr(source2, rs2);
switch (opc) {
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLW:
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SLL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shl_tl(source1, source1, source2);
- break;
- case OPC_RISC_SLT:
- tcg_gen_setcond_tl(TCG_COND_LT, source1, source1, source2);
- break;
- case OPC_RISC_SLTU:
- tcg_gen_setcond_tl(TCG_COND_LTU, source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRLW:
- /* clear upper 32 */
- tcg_gen_ext32u_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRL:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_shr_tl(source1, source1, source2);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SRAW:
- /* first, trick to get it to act like working on 32 bits (get rid of
- upper 32, sign extend to fill space) */
- tcg_gen_ext32s_tl(source1, source1);
- tcg_gen_andi_tl(source2, source2, 0x1F);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
-#endif
- case OPC_RISC_SRA:
- tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
- tcg_gen_sar_tl(source1, source1, source2);
- break;
CASE_OP_32_64(OPC_RISC_MUL):
if (!has_ext(ctx, RVM)) {
goto do_illegal;
@@ -742,6 +701,24 @@ static bool trans_arith(DisasContext *ctx, arg_r *a,
return true;
}
+static bool gen_shift(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1 = tcg_temp_new();
+ TCGv source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"
--
2.20.1
next prev parent reply other threads:[~2019-02-22 14:12 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-22 14:09 [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 03/34] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 04/34] target/riscv: Convert RV64I " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 05/34] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 06/34] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 07/34] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 08/34] target/riscv: Convert RVXM " Bastian Koppelmann
2019-02-22 14:09 ` [Qemu-devel] [PATCH v8 09/34] target/riscv: Convert RV32A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 10/34] target/riscv: Convert RV64A " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 11/34] target/riscv: Convert RV32F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 12/34] target/riscv: Convert RV64F " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 13/34] target/riscv: Convert RV32D " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 14/34] target/riscv: Convert RV64D " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 15/34] target/riscv: Convert RV priv " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 16/34] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 17/34] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 18/34] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 19/34] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 21/34] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 22/34] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-02-22 14:10 ` Bastian Koppelmann [this message]
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 27/34] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 28/34] target/riscv: Remove gen_system() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 29/34] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 30/34] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 33/34] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-02-22 14:10 ` [Qemu-devel] [PATCH v8 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-02-22 23:16 ` [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree Alistair Francis
2019-02-27 17:55 ` no-reply
2019-02-28 8:37 ` Thomas Huth
2019-02-28 9:06 ` Paolo Bonzini
2019-02-27 18:19 ` no-reply
2019-02-27 18:36 ` no-reply
2019-02-27 18:41 ` no-reply
2019-02-27 18:53 ` no-reply
2019-02-27 18:57 ` no-reply
2019-02-27 19:03 ` no-reply
2019-02-27 19:08 ` no-reply
2019-02-27 19:14 ` no-reply
2019-02-27 19:19 ` no-reply
2019-02-27 19:25 ` no-reply
2019-02-27 19:29 ` no-reply
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2019-02-27 19:57 ` no-reply
2019-02-27 20:17 ` no-reply
2019-02-27 20:23 ` no-reply
2019-02-27 20:27 ` no-reply
2019-02-27 20:33 ` no-reply
2019-02-27 20:38 ` no-reply
2019-02-27 20:43 ` no-reply
2019-02-27 20:47 ` no-reply
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2019-02-27 20:56 ` no-reply
2019-02-27 21:01 ` no-reply
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