[Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2

[Richard Henderson <richard.henderson@linaro.org>]

This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 1 +
 target/arm/helper.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 84ae6849c2..c57f8e9ba8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -863,6 +863,7 @@ struct ARMCPU {
     uint32_t reset_sctlr;
     uint32_t id_pfr0;
     uint32_t id_pfr1;
+    uint32_t id_pfr2;
     uint32_t id_dfr0;
     uint64_t pmceid0;
     uint64_t pmceid1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a018eb23fe..8903cc13d8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = 0 },
-            { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
-              .resetvalue = 0 },
+              .resetvalue = cpu->id_pfr2 },
             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.17.2