From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:48640) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gyWTG-0003qO-Re for qemu-devel@nongnu.org; Tue, 26 Feb 2019 01:44:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gyWTG-0000rM-1B for qemu-devel@nongnu.org; Tue, 26 Feb 2019 01:44:06 -0500 Received: from mga06.intel.com ([134.134.136.31]:26985) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gyWTF-0000Wk-P8 for qemu-devel@nongnu.org; Tue, 26 Feb 2019 01:44:05 -0500 From: Yang Weijiang Date: Mon, 25 Feb 2019 21:37:43 +0800 Message-Id: <20190225133744.7095-5-weijiang.yang@intel.com> In-Reply-To: <20190225133744.7095-1-weijiang.yang@intel.com> References: <20190225133744.7095-1-weijiang.yang@intel.com> Subject: [Qemu-devel] [PATCH v3 4/5] Report CPUID xsave area support for CET. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: pbonzini@redhat.com, cdupontd@redhat.com, rkrcmar@redhat.com, qemu-devel@nongnu.org, mst@redhat.com Cc: Yang Weijiang , Zhang Yi CPUID bit definition as below: CPUID.(EAX=d, ECX=1):ECX.CET_U(bit 11): user mode state CPUID.(EAX=d, ECX=1):ECX.CET_S(bit 12): kernel mode state Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d8c36e0f2f..15e2d5e009 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4399,12 +4399,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ebx = xsave_area_size(env->xcr0); } else if (count == 1) { *eax = env->features[FEAT_XSAVE]; + *ecx = env->features[FEAT_XSAVE_SV_LO]; + *edx = env->features[FEAT_XSAVE_SV_HI]; + *ebx = xsave_area_size_compacted(x86_cpu_xsave_components(cpu) | + x86_cpu_xsave_sv_components(cpu)); } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { if ((x86_cpu_xsave_components(cpu) >> count) & 1) { const ExtSaveArea *esa = &x86_ext_save_areas[count]; *eax = esa->size; *ebx = esa->offset; } + if ((x86_cpu_xsave_sv_components(cpu) >> count) & 1) { + const ExtSaveArea *esa_sv = &x86_ext_save_areas[count]; + *eax = esa_sv->size; + *ebx = 0; + *ecx = 1; + } } break; } -- 2.17.1