From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/16] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
Date: Thu, 28 Feb 2019 11:08:24 +0000 [thread overview]
Message-ID: <20190228110835.16159-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190228110835.16159-1-peter.maydell@linaro.org>
The iotkit-sysctl device has a register it names INITSVRTOR0.
This is actually a typo present in the IoTKit documentation
and also in part of the SSE-200 documentation: it should be
INITSVTOR0 because it is specifying the initial value of the
Secure VTOR register in the CPU. Correct the typo.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
---
include/hw/misc/iotkit-sysctl.h | 2 +-
hw/misc/iotkit-sysctl.c | 16 ++++++++--------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index e36613cb5ee..17a145517a4 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -41,7 +41,7 @@ typedef struct IoTKitSysCtl {
uint32_t reset_syndrome;
uint32_t reset_mask;
uint32_t gretreg;
- uint32_t initsvrtor0;
+ uint32_t initsvtor0;
uint32_t cpuwait;
uint32_t wicctrl;
} IoTKitSysCtl;
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index a21d8bd6789..8c85aea9309 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -33,7 +33,7 @@ REG32(RESET_MASK, 0x104)
REG32(SWRESET, 0x108)
FIELD(SWRESET, SWRESETREQ, 9, 1)
REG32(GRETREG, 0x10c)
-REG32(INITSVRTOR0, 0x110)
+REG32(INITSVTOR0, 0x110)
REG32(CPUWAIT, 0x118)
REG32(BUSWAIT, 0x11c)
REG32(WICCTRL, 0x120)
@@ -76,8 +76,8 @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
case A_GRETREG:
r = s->gretreg;
break;
- case A_INITSVRTOR0:
- r = s->initsvrtor0;
+ case A_INITSVTOR0:
+ r = s->initsvtor0;
break;
case A_CPUWAIT:
r = s->cpuwait;
@@ -145,9 +145,9 @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
*/
s->gretreg = value;
break;
- case A_INITSVRTOR0:
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
- s->initsvrtor0 = value;
+ case A_INITSVTOR0:
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
+ s->initsvtor0 = value;
break;
case A_CPUWAIT:
qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
@@ -206,7 +206,7 @@ static void iotkit_sysctl_reset(DeviceState *dev)
s->reset_syndrome = 1;
s->reset_mask = 0;
s->gretreg = 0;
- s->initsvrtor0 = 0x10000000;
+ s->initsvtor0 = 0x10000000;
s->cpuwait = 0;
s->wicctrl = 0;
}
@@ -230,7 +230,7 @@ static const VMStateDescription iotkit_sysctl_vmstate = {
VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
VMSTATE_UINT32(gretreg, IoTKitSysCtl),
- VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
+ VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
VMSTATE_END_OF_LIST()
--
2.20.1
next prev parent reply other threads:[~2019-02-28 11:09 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-28 11:08 [Qemu-devel] [PULL 00/16] target-arm queue Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 04/16] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() Peter Maydell
2019-02-28 11:08 ` Peter Maydell [this message]
2019-02-28 11:08 ` [Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR* Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code" Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64 Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32 Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max Peter Maydell
2019-02-28 11:08 ` [Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT Peter Maydell
2019-02-28 11:25 ` [Qemu-devel] [PULL 00/16] target-arm queue no-reply
2019-02-28 19:03 ` Peter Maydell
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