From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Peer Adelt <peer.adelt@hni.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 20/34] target/riscv: Remove manual decoding from gen_branch()
Date: Fri, 1 Mar 2019 13:49:31 -0800 [thread overview]
Message-ID: <20190301214945.4353-21-palmer@sifive.com> (raw)
In-Reply-To: <20190301214945.4353-1-palmer@sifive.com>
From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
target/riscv/translate.c | 47 -------------------------
2 files changed, 33 insertions(+), 60 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 631a88906bce..ae4b0a2bcb78 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
-static bool trans_beq(DisasContext *ctx, arg_beq *a)
+static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
- gen_branch(ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
+ TCGLabel *l = gen_new_label();
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+ gen_get_gpr(source2, a->rs2);
+
+ tcg_gen_brcond_tl(cond, source1, source2, l);
+ gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+ gen_set_label(l); /* branch taken */
+
+ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
+ /* misaligned */
+ gen_exception_inst_addr_mis(ctx);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
+ }
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+
return true;
}
+static bool trans_beq(DisasContext *ctx, arg_beq *a)
+{
+ return gen_branch(ctx, a, TCG_COND_EQ);
+}
+
static bool trans_bne(DisasContext *ctx, arg_bne *a)
{
- gen_branch(ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_NE);
}
static bool trans_blt(DisasContext *ctx, arg_blt *a)
{
- gen_branch(ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LT);
}
static bool trans_bge(DisasContext *ctx, arg_bge *a)
{
- gen_branch(ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GE);
}
static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
{
- gen_branch(ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_LTU);
}
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
{
-
- gen_branch(ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
- return true;
+ return gen_branch(ctx, a, TCG_COND_GEU);
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9dee2ec24287..a3d5cdbad82d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -531,53 +531,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
- target_long bimm)
-{
- TCGLabel *l = gen_new_label();
- TCGv source1, source2;
- source1 = tcg_temp_new();
- source2 = tcg_temp_new();
- gen_get_gpr(source1, rs1);
- gen_get_gpr(source2, rs2);
-
- switch (opc) {
- case OPC_RISC_BEQ:
- tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
- break;
- case OPC_RISC_BNE:
- tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
- break;
- case OPC_RISC_BLT:
- tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
- break;
- case OPC_RISC_BGE:
- tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
- break;
- case OPC_RISC_BLTU:
- tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
- break;
- case OPC_RISC_BGEU:
- tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
- break;
- default:
- gen_exception_illegal(ctx);
- return;
- }
- tcg_temp_free(source1);
- tcg_temp_free(source2);
-
- gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
- gen_set_label(l); /* branch taken */
- if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
- /* misaligned */
- gen_exception_inst_addr_mis(ctx);
- } else {
- gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
- }
- ctx->base.is_jmp = DISAS_NORETURN;
-}
-
static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
--
2.18.1
next prev parent reply other threads:[~2019-03-01 21:50 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-01 21:49 [Qemu-devel] [PULL] target/riscv: Convert to decodetree Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 03/34] target/riscv: Convert RV32I load/store " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 04/34] target/riscv: Convert RV64I " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 05/34] target/riscv: Convert RVXI arithmetic " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 06/34] target/riscv: Convert RVXI fence " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 07/34] target/riscv: Convert RVXI csr " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 08/34] target/riscv: Convert RVXM " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 09/34] target/riscv: Convert RV32A " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 10/34] target/riscv: Convert RV64A " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 11/34] target/riscv: Convert RV32F " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 12/34] target/riscv: Convert RV64F " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 13/34] target/riscv: Convert RV32D " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 14/34] target/riscv: Convert RV64D " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 15/34] target/riscv: Convert RV priv " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 16/34] target/riscv: Convert quadrant 0 of RVXC " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 17/34] target/riscv: Convert quadrant 1 " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 18/34] target/riscv: Convert quadrant 2 " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 19/34] target/riscv: Remove gen_jalr() Palmer Dabbelt
2019-03-01 21:49 ` Palmer Dabbelt [this message]
2019-03-01 21:49 ` [Qemu-devel] [PULL 21/34] target/riscv: Remove manual decoding from gen_load() Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 22/34] target/riscv: Remove manual decoding from gen_store() Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 28/34] target/riscv: Remove gen_system() Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G() Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 33/34] target/riscv: Splice remaining compressed insn pairs " Palmer Dabbelt
2019-03-01 21:49 ` [Qemu-devel] [PULL 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators Palmer Dabbelt
2019-03-04 11:02 ` [Qemu-devel] [PULL] target/riscv: Convert to decodetree Peter Maydell
2019-03-04 12:52 ` Bastian Koppelmann
2019-03-04 15:25 ` Bastian Koppelmann
2019-03-04 19:30 ` Richard Henderson
2019-03-04 21:46 ` Palmer Dabbelt
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