From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:49627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzq30-00030y-2l for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzq2p-0002Bx-TO for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:17 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:35286) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzq2i-0001qf-3C for qemu-devel@nongnu.org; Fri, 01 Mar 2019 16:50:14 -0500 Received: by mail-pl1-x635.google.com with SMTP id p19so12093155plo.2 for ; Fri, 01 Mar 2019 13:50:07 -0800 (PST) Date: Fri, 1 Mar 2019 13:49:17 -0800 Message-Id: <20190301214945.4353-7-palmer@sifive.com> In-Reply-To: <20190301214945.4353-1-palmer@sifive.com> References: <20190301214945.4353-1-palmer@sifive.com> From: Palmer Dabbelt Subject: [Qemu-devel] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Bastian Koppelmann , Peer Adelt , Palmer Dabbelt From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvi.inc.c | 19 +++++++++++++++++++ target/riscv/translate.c | 12 ------------ 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1f5bf1f6f97d..804b721ca51e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r +fence ---- pred:4 succ:4 ----- 000 ----- 0001111 +fence_i ---- ---- ---- ----- 001 ----- 0001111 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c index 136fa54d0655..973d6371df85 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a) return true; } #endif + +static bool trans_fence(DisasContext *ctx, arg_fence *a) +{ + /* FENCE is a full memory barrier. */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) +{ + /* + * FENCE_I is a no-op in QEMU, + * however we need to end the translation block + */ + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1ae84dcd5992..f720746cb791 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1950,18 +1950,6 @@ static void decode_RV32_64G(DisasContext *ctx) gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2, GET_RM(ctx->opcode)); break; - case OPC_RISC_FENCE: - if (ctx->opcode & 0x1000) { - /* FENCE_I is a no-op in QEMU, - * however we need to end the translation block */ - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); - tcg_gen_exit_tb(NULL, 0); - ctx->base.is_jmp = DISAS_NORETURN; - } else { - /* FENCE is a full memory barrier. */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - } - break; case OPC_RISC_SYSTEM: gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, (ctx->opcode & 0xFFF00000) >> 20); -- 2.18.1