From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 07/27] ppc/pnv: introduce a new dt_populate() operation to the chip model
Date: Wed, 6 Mar 2019 09:50:12 +0100 [thread overview]
Message-ID: <20190306085032.15744-8-clg@kaod.org> (raw)
In-Reply-To: <20190306085032.15744-1-clg@kaod.org>
The POWER9 and POWER8 processors have a different set of devices and a
different device tree layout.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 1 +
hw/ppc/pnv.c | 27 +++++++++++++++++++++++++--
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index ebbb3d0e9aa7..fa9ec50fd5be 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -102,6 +102,7 @@ typedef struct PnvChipClass {
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
+ void (*dt_populate)(PnvChip *chip, void *fdt);
} PnvChipClass;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a7ec76dbd6c7..087541a91a72 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -267,7 +267,7 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
g_free(reg);
}
-static void pnv_dt_chip(PnvChip *chip, void *fdt)
+static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
const char *typename = pnv_chip_core_typename(chip);
size_t typesize = object_type_get_instance_size(typename);
@@ -289,6 +289,25 @@ static void pnv_dt_chip(PnvChip *chip, void *fdt)
}
}
+static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
+{
+ const char *typename = pnv_chip_core_typename(chip);
+ size_t typesize = object_type_get_instance_size(typename);
+ int i;
+
+ pnv_dt_xscom(chip, fdt, 0);
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
+
+ pnv_dt_core(chip, pnv_core, fdt);
+ }
+
+ if (chip->ram_size) {
+ pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
+ }
+}
+
static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
{
uint32_t io_base = d->ioport_id;
@@ -474,7 +493,7 @@ static void *pnv_dt_create(MachineState *machine)
/* Populate device tree for each chip */
for (i = 0; i < pnv->num_chips; i++) {
- pnv_dt_chip(pnv->chips[i], fdt);
+ PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
}
/* Populate ISA devices on chip 0 */
@@ -858,6 +877,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->isa_create = pnv_chip_power8_isa_create;
+ k->dt_populate = pnv_chip_power8_dt_populate;
k->xscom_base = 0x003fc0000000000ull;
dc->desc = "PowerNV Chip POWER8E";
@@ -876,6 +896,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->isa_create = pnv_chip_power8_isa_create;
+ k->dt_populate = pnv_chip_power8_dt_populate;
k->xscom_base = 0x003fc0000000000ull;
dc->desc = "PowerNV Chip POWER8";
@@ -894,6 +915,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->core_pir = pnv_chip_core_pir_p8;
k->intc_create = pnv_chip_power8_intc_create;
k->isa_create = pnv_chip_power8nvl_isa_create;
+ k->dt_populate = pnv_chip_power8_dt_populate;
k->xscom_base = 0x003fc0000000000ull;
dc->desc = "PowerNV Chip POWER8NVL";
@@ -954,6 +976,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->core_pir = pnv_chip_core_pir_p9;
k->intc_create = pnv_chip_power9_intc_create;
k->isa_create = pnv_chip_power9_isa_create;
+ k->dt_populate = pnv_chip_power9_dt_populate;
k->xscom_base = 0x00603fc00000000ull;
dc->desc = "PowerNV Chip POWER9";
--
2.20.1
next prev parent reply other threads:[~2019-03-06 8:51 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-06 8:50 [Qemu-devel] [PATCH 00/27] ppc: add POWER9 support to the PowerNV platform Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 01/27] ppc/xive: hardwire the Physical CAM line of the thread context Cédric Le Goater
2019-03-07 1:19 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 02/27] ppc: externalize ppc_get_vcpu_by_pir() Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 03/27] ppc/xive: export the TIMA memory accessors Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 04/27] ppc/pnv: export the xive_router_notify() routine Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 05/27] ppc/pnv: change the CPU machine_data presenter type to Object * Cédric Le Goater
2019-03-07 1:36 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 06/27] ppc/pnv: add a XIVE interrupt controller model for POWER9 Cédric Le Goater
2019-03-07 1:37 ` David Gibson
2019-03-06 8:50 ` Cédric Le Goater [this message]
2019-03-07 1:44 ` [Qemu-devel] [PATCH 07/27] ppc/pnv: introduce a new dt_populate() operation to the chip model David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 08/27] ppc/pnv: introduce a new pic_print_info() " Cédric Le Goater
2019-03-07 1:46 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 09/27] ppc/xive: activate HV support Cédric Le Goater
2019-03-07 1:48 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 10/27] ppc/xive: Make XIVE generate the proper interrupt types Cédric Le Goater
2019-03-07 3:29 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 11/27] ppc/pnv: fix logging primitives using Ox Cédric Le Goater
2019-03-07 3:30 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 12/27] ppc/pnv: psi: add a PSIHB_REG macro Cédric Le Goater
2019-03-07 3:30 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 13/27] ppc/pnv: psi: add a reset handler Cédric Le Goater
2019-03-07 3:32 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 14/27] ppc/pnv: add a PSI bridge model class Cédric Le Goater
2019-03-07 4:05 ` David Gibson
2019-03-07 4:08 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 15/27] ppc/pnv: add a PSI bridge model for POWER9 Cédric Le Goater
2019-03-07 4:10 ` David Gibson
2019-03-07 6:37 ` Cédric Le Goater
2019-03-07 22:33 ` Cédric Le Goater
2019-03-08 0:17 ` David Gibson
2019-03-08 6:45 ` Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 16/27] ppc/pnv: lpc: fix OPB address ranges Cédric Le Goater
2019-03-07 4:11 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 17/27] ppc/pnv: add a LPC Controller model class Cédric Le Goater
2019-03-07 4:12 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 18/27] ppc/pnv: add a LPC Controller model for POWER9 Cédric Le Goater
2019-03-07 4:18 ` David Gibson
2019-03-07 7:07 ` Cédric Le Goater
2019-03-08 0:19 ` David Gibson
2019-03-08 6:49 ` Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 19/27] ppc/pnv: add SerIRQ routing registers Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 20/27] ppc/pnv: add a OCC model class Cédric Le Goater
2019-03-07 4:26 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 21/27] ppc/pnv: add a OCC model for POWER9 Cédric Le Goater
2019-03-07 4:27 ` David Gibson
2019-03-07 7:47 ` Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 22/27] ppc/pnv: extend XSCOM core support " Cédric Le Goater
2019-03-07 4:28 ` David Gibson
2019-03-06 8:50 ` [Qemu-devel] [PATCH 23/27] ppc/pnv: POWER9 XSCOM quad support Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 24/27] ppc/pnv: activate XSCOM tests for POWER9 Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 25/27] ppc/pnv: add more dummy XSCOM addresses Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 26/27] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 Cédric Le Goater
2019-03-06 8:50 ` [Qemu-devel] [PATCH 27/27] target/ppc: add HV support for POWER9 Cédric Le Goater
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