From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: david@redhat.com
Subject: [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64}
Date: Thu, 7 Mar 2019 06:41:18 -0800 [thread overview]
Message-ID: <20190307144126.31847-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190307144126.31847-1-richard.henderson@linaro.org>
From: David Hildenbrand <david@redhat.com>
Will be helpful for s390x. Input 128 bit and output 64 bit only,
which is sufficient for now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190225154204.26751-1-david@redhat.com>
[rth: Add matching tcg_gen_extract2_i32.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 6 ++++++
tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d3e51b15af..1f1824c30a 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -308,6 +308,8 @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
unsigned int ofs, unsigned int len);
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
+ unsigned int ofs);
void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
@@ -501,6 +503,8 @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
unsigned int ofs, unsigned int len);
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
+ unsigned int ofs);
void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
@@ -1068,6 +1072,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
+#define tcg_gen_extract2_tl tcg_gen_extract2_i64
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
@@ -1178,6 +1183,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
+#define tcg_gen_extract2_tl tcg_gen_extract2_i32
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 1bd7ef24af..7c56c92c8e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -809,6 +809,28 @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
tcg_gen_sari_i32(ret, ret, 32 - len);
}
+/*
+ * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
+ * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
+ */
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
+ unsigned int ofs)
+{
+ tcg_debug_assert(ofs <= 32);
+ if (ofs == 0) {
+ tcg_gen_mov_i32(ret, al);
+ } else if (ofs == 32) {
+ tcg_gen_mov_i32(ret, ah);
+ } else if (al == ah) {
+ tcg_gen_rotri_i32(ret, al, ofs);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_shri_i32(t0, al, ofs);
+ tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
+ tcg_temp_free_i32(t0);
+ }
+}
+
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
{
@@ -2297,6 +2319,28 @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
tcg_gen_sari_i64(ret, ret, 64 - len);
}
+/*
+ * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
+ * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
+ */
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
+ unsigned int ofs)
+{
+ tcg_debug_assert(ofs <= 64);
+ if (ofs == 0) {
+ tcg_gen_mov_i64(ret, al);
+ } else if (ofs == 64) {
+ tcg_gen_mov_i64(ret, ah);
+ } else if (al == ah) {
+ tcg_gen_rotri_i64(ret, al, ofs);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_shri_i64(t0, al, ofs);
+ tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
+ tcg_temp_free_i64(t0);
+ }
+}
+
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
{
--
2.17.2
next prev parent reply other threads:[~2019-03-07 14:41 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-07 14:41 [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} Richard Henderson
2019-03-07 14:41 ` Richard Henderson [this message]
2019-03-08 23:19 ` [Qemu-devel] [PATCH 1/9] tcg: Implement tcg_gen_extract2_{i32, i64} Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 2/9] tcg: Add INDEX_op_extract2_{i32,i64} Richard Henderson
2019-03-07 15:19 ` David Hildenbrand
2019-03-08 23:28 ` Philippe Mathieu-Daudé
2019-03-09 16:37 ` Richard Henderson
[not found] ` <CAFEAcA8JwtiBSgUg_8kg52GETGd3vbX86nvziXa6ZyvqDPLt5g@mail.gmail.com>
2019-04-03 11:37 ` Richard Henderson
2019-04-03 11:56 ` Peter Maydell
2019-04-13 8:31 ` Richard Henderson
2019-04-13 8:31 ` Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 3/9] tcg: Use extract2 in tcg_gen_shifti_i64 Richard Henderson
2019-03-09 1:00 ` Philippe Mathieu-Daudé
2019-03-09 20:30 ` Aleksandar Markovic
2019-03-10 6:43 ` Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 4/9] tcg: Use extract2 in tcg_gen_deposit_{i32, i64} Richard Henderson
2019-03-09 0:36 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 5/9] tcg/i386: Support INDEX_op_extract2_{i32, i64} Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 6/9] tcg/arm: Support INDEX_op_extract2_i32 Richard Henderson
2019-03-09 0:11 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 7/9] tcg/aarch64: Support INDEX_op_extract2_{i32, i64} Richard Henderson
2019-03-08 23:41 ` Philippe Mathieu-Daudé
2019-03-07 14:41 ` [Qemu-devel] [PATCH 8/9] target/arm: Use extract2 for EXTR Richard Henderson
2019-03-07 14:41 ` [Qemu-devel] [PATCH 9/9] target/arm: Simplify BFXIL expansion Richard Henderson
2019-03-09 0:45 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2019-03-07 15:23 ` [Qemu-devel] [PATCH 0/9] tcg: Add tcg_gen_extract2_{i32,i64} no-reply
2019-03-07 15:47 ` no-reply
2019-03-08 23:23 ` no-reply
2019-03-08 23:45 ` no-reply
2019-03-09 0:16 ` no-reply
2019-03-09 0:49 ` no-reply
2019-04-09 18:53 ` David Hildenbrand
2019-04-09 18:53 ` David Hildenbrand
2019-04-09 19:02 ` Richard Henderson
2019-04-09 19:02 ` Richard Henderson
2019-04-09 19:05 ` David Hildenbrand
2019-04-09 19:05 ` David Hildenbrand
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