From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v4 17/22] target/arm: Set PSTATE.TCO on exception entry
Date: Thu, 7 Mar 2019 09:04:35 -0800 [thread overview]
Message-ID: <20190307170440.3113-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org>
R0085 specifies that exception handlers begin with tag checks overridden.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Only set if MTE feature present.
---
target/arm/helper.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c8773a5528..a529d30700 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9628,6 +9628,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
target_ulong addr = env->cp15.vbar_el[new_el];
unsigned int new_mode = aarch64_pstate_mode(new_el, true);
unsigned int cur_el = arm_current_el(env);
+ unsigned int new_pstate;
/*
* Note that new_el can never be 0. If cur_el is 0, then
@@ -9721,7 +9722,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
env->elr_el[new_el]);
- pstate_write(env, PSTATE_DAIF | new_mode);
+ new_pstate = new_mode | PSTATE_DAIF;
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ new_pstate |= PSTATE_TCO;
+ }
+ pstate_write(env, new_pstate);
env->aarch64 = 1;
aarch64_restore_sp(env, new_el);
--
2.17.2
next prev parent reply other threads:[~2019-03-07 17:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-07 17:04 [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 01/22] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 02/22] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 03/22] target/arm: Add MTE system registers Richard Henderson
2019-03-08 10:31 ` Laurent Desnogues
2019-03-08 10:37 ` Laurent Desnogues
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 04/22] target/arm: Add helper_mte_check{1, 2} Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 05/22] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 06/22] target/arm: Implement the IRG instruction Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 07/22] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 08/22] target/arm: Implement the GMI instruction Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 09/22] target/arm: Implement the SUBP instruction Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 10/22] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 11/22] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 12/22] target/arm: Implement the STGP instruction Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 13/22] target/arm: Implement the LDGM and STGM instructions Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 14/22] target/arm: Implement the access tag cache flushes Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 15/22] target/arm: Clean address for DC ZVA Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 16/22] target/arm: Implement data cache set allocation tags Richard Henderson
2019-03-07 17:04 ` Richard Henderson [this message]
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 18/22] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 19/22] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2019-07-22 16:03 ` Peter Maydell
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag physical address space Richard Henderson
2019-07-19 15:48 ` Peter Maydell
2019-07-19 21:31 ` Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 21/22] target/arm: Add allocation tag storage for system mode Richard Henderson
2019-03-07 17:04 ` [Qemu-devel] [PATCH v4 22/22] target/arm: Enable MTE Richard Henderson
2019-03-07 17:35 ` [Qemu-devel] [PATCH v4 00/22] target/arm: Implement ARMv8.5-MemTag, system mode no-reply
2019-03-08 18:40 ` no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190307170440.3113-18-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).