From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:58911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1wSD-0006Pr-Qe for qemu-devel@nongnu.org; Thu, 07 Mar 2019 12:05:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1wSA-0004kc-Mu for qemu-devel@nongnu.org; Thu, 07 Mar 2019 12:05:07 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:40279) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h1wS7-0004Q3-S6 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 12:05:04 -0500 Received: by mail-pf1-x441.google.com with SMTP id h1so11900004pfo.7 for ; Thu, 07 Mar 2019 09:04:53 -0800 (PST) From: Richard Henderson Date: Thu, 7 Mar 2019 09:04:26 -0800 Message-Id: <20190307170440.3113-9-richard.henderson@linaro.org> In-Reply-To: <20190307170440.3113-1-richard.henderson@linaro.org> References: <20190307170440.3113-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v4 08/22] target/arm: Implement the GMI instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6ad23bf9ee..3b78e19279 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,4 @@ DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 7aca5b074f..e60c6f48eb 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -220,3 +220,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 181692cd1b..e756985982 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5316,6 +5316,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; -- 2.17.2