From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: groug@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
lvivier@redhat.com,
Suraj Jitindar Singh <sjitindarsingh@gmail.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 10/60] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST
Date: Sun, 10 Mar 2019 19:26:13 +1100 [thread overview]
Message-ID: <20190310082703.1245-11-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20190310082703.1245-1-david@gibson.dropbear.id.au>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch. Some revisions of
hardware may have a hardware accelerated flush, in which case the
software flush can be shortened. This cap is used to set the
availability of such hardware acceleration for the count cache flush
routine.
The availability of such hardware acceleration is indicated by the
H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics
returned from the KVM_PPC_GET_CPU_CHAR ioctl.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Message-Id: <20190301031912.28809-2-sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 2 ++
hw/ppc/spapr_caps.c | 25 +++++++++++++++++++++++++
hw/ppc/spapr_hcall.c | 3 +++
include/hw/ppc/spapr.h | 5 ++++-
target/ppc/kvm.c | 14 ++++++++++++++
target/ppc/kvm_ppc.h | 6 ++++++
6 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 8e24d7dc50..37fd7a1411 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2097,6 +2097,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_cap_nested_kvm_hv,
&vmstate_spapr_dtb,
&vmstate_spapr_cap_large_decr,
+ &vmstate_spapr_cap_ccf_assist,
NULL
}
};
@@ -4312,6 +4313,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */
smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
+ smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
spapr_caps_add_properties(smc, &error_abort);
smc->irq = &spapr_irq_xics;
smc->dr_phb_enabled = true;
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 74a48a423a..f03f2f64e7 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -436,6 +436,21 @@ static void cap_large_decr_cpu_apply(sPAPRMachineState *spapr,
ppc_store_lpcr(cpu, lpcr);
}
+static void cap_ccf_assist_apply(sPAPRMachineState *spapr, uint8_t val,
+ Error **errp)
+{
+ uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
+
+ if (tcg_enabled() && val) {
+ /* TODO - for now only allow broken for TCG */
+ error_setg(errp,
+"Requested count cache flush assist capability level not supported by tcg, try cap-ccf-assist=off");
+ } else if (kvm_enabled() && (val > kvm_val)) {
+ error_setg(errp,
+"Requested count cache flush assist capability level not supported by kvm, try cap-ccf-assist=off");
+ }
+}
+
sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
[SPAPR_CAP_HTM] = {
.name = "htm",
@@ -525,6 +540,15 @@ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
.apply = cap_large_decr_apply,
.cpu_apply = cap_large_decr_cpu_apply,
},
+ [SPAPR_CAP_CCF_ASSIST] = {
+ .name = "ccf-assist",
+ .description = "Count Cache Flush Assist via HW Instruction",
+ .index = SPAPR_CAP_CCF_ASSIST,
+ .get = spapr_cap_get_bool,
+ .set = spapr_cap_set_bool,
+ .type = "bool",
+ .apply = cap_ccf_assist_apply,
+ },
};
static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
@@ -659,6 +683,7 @@ SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC);
SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS);
SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
+SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
void spapr_caps_init(sPAPRMachineState *spapr)
{
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 4aa8036fc0..8bfdddc964 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1693,6 +1693,7 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
+ uint8_t count_cache_flush_assist = spapr_get_cap(spapr, SPAPR_CAP_CCF_ASSIST);
switch (safe_cache) {
case SPAPR_CAP_WORKAROUND:
@@ -1733,6 +1734,8 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
break;
case SPAPR_CAP_WORKAROUND:
behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
+ if (count_cache_flush_assist)
+ characteristics |= H_CPU_CHAR_BCCTR_FLUSH_ASSIST;
break;
default: /* broken */
assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index a7f3b1bfdd..ff1bd60615 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -76,8 +76,10 @@ typedef enum {
#define SPAPR_CAP_NESTED_KVM_HV 0x07
/* Large Decrementer */
#define SPAPR_CAP_LARGE_DECREMENTER 0x08
+/* Count Cache Flush Assist HW Instruction */
+#define SPAPR_CAP_CCF_ASSIST 0x09
/* Num Caps */
-#define SPAPR_CAP_NUM (SPAPR_CAP_LARGE_DECREMENTER + 1)
+#define SPAPR_CAP_NUM (SPAPR_CAP_CCF_ASSIST + 1)
/*
* Capability Values
@@ -838,6 +840,7 @@ extern const VMStateDescription vmstate_spapr_cap_sbbc;
extern const VMStateDescription vmstate_spapr_cap_ibs;
extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
extern const VMStateDescription vmstate_spapr_cap_large_decr;
+extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
{
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 7a7a5adee3..e0f0de0ce0 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -90,6 +90,7 @@ static int cap_ppc_pvr_compat;
static int cap_ppc_safe_cache;
static int cap_ppc_safe_bounds_check;
static int cap_ppc_safe_indirect_branch;
+static int cap_ppc_count_cache_flush_assist;
static int cap_ppc_nested_kvm_hv;
static int cap_large_decr;
@@ -2406,6 +2407,13 @@ static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
return 0;
}
+static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
+{
+ if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
+ return 1;
+ return 0;
+}
+
static void kvmppc_get_cpu_characteristics(KVMState *s)
{
struct kvm_ppc_cpu_char c;
@@ -2428,6 +2436,7 @@ static void kvmppc_get_cpu_characteristics(KVMState *s)
cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
+ cap_ppc_count_cache_flush_assist = parse_cap_ppc_count_cache_flush_assist(c);
}
int kvmppc_get_cap_safe_cache(void)
@@ -2445,6 +2454,11 @@ int kvmppc_get_cap_safe_indirect_branch(void)
return cap_ppc_safe_indirect_branch;
}
+int kvmppc_get_cap_count_cache_flush_assist(void)
+{
+ return cap_ppc_count_cache_flush_assist;
+}
+
bool kvmppc_has_cap_nested_kvm_hv(void)
{
return !!cap_ppc_nested_kvm_hv;
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index a79835bd14..2937b36cae 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -62,6 +62,7 @@ bool kvmppc_has_cap_mmu_hash_v3(void);
int kvmppc_get_cap_safe_cache(void);
int kvmppc_get_cap_safe_bounds_check(void);
int kvmppc_get_cap_safe_indirect_branch(void);
+int kvmppc_get_cap_count_cache_flush_assist(void);
bool kvmppc_has_cap_nested_kvm_hv(void);
int kvmppc_set_cap_nested_kvm_hv(int enable);
int kvmppc_get_cap_large_decr(void);
@@ -324,6 +325,11 @@ static inline int kvmppc_get_cap_safe_indirect_branch(void)
return 0;
}
+static inline int kvmppc_get_cap_count_cache_flush_assist(void)
+{
+ return 0;
+}
+
static inline bool kvmppc_has_cap_nested_kvm_hv(void)
{
return false;
--
2.20.1
next prev parent reply other threads:[~2019-03-10 8:27 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-10 8:26 [Qemu-devel] [PULL 00/60] ppc-for-4.0 queue 20190310 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 01/60] vfio/spapr: Fix indirect levels calculation David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 02/60] vfio/spapr: Rename local systempagesize variable David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 03/60] spapr: Simulate CAS for qtest David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 04/60] Revert "spapr: support memory unplug for qtest" David Gibson
2019-03-11 10:52 ` Greg Kurz
2019-03-12 1:08 ` David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 05/60] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 06/60] target/ppc: Implement large decrementer support for TCG David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 07/60] target/ppc: Implement large decrementer support for KVM David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 08/60] target/ppc/spapr: Enable the large decrementer for pseries-4.0 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 09/60] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS David Gibson
2019-03-10 8:26 ` David Gibson [this message]
2019-03-10 8:26 ` [Qemu-devel] [PULL 11/60] target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 12/60] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 13/60] target/ppc: Move exception vector offset computation into a function David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 14/60] target/ppc: Move handling of hardware breakpoints to a separate function David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 15/60] target/ppc: Refactor kvm_handle_debug David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 16/60] PPC: E500: Update u-boot to v2019.01 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 17/60] target/ppc/spapr: Clear partition table entry when allocating hash table David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 18/60] spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit) David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 19/60] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 20/60] PPC: E500: Add FSL I2C controller and integrate RTC with it David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 21/60] ppc/xive: hardwire the Physical CAM line of the thread context David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 22/60] ppc: externalize ppc_get_vcpu_by_pir() David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 23/60] ppc/xive: export the TIMA memory accessors David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 24/60] ppc/pnv: export the xive_router_notify() routine David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 25/60] ppc/pnv: change the CPU machine_data presenter type to Object * David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 26/60] ppc/pnv: add a XIVE interrupt controller model for POWER9 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 27/60] ppc/pnv: introduce a new dt_populate() operation to the chip model David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 28/60] ppc/pnv: introduce a new pic_print_info() " David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 29/60] ppc/xive: activate HV support David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 30/60] ppc/pnv: fix logging primitives using Ox David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 31/60] ppc/pnv: psi: add a PSIHB_REG macro David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 32/60] ppc/pnv: psi: add a reset handler David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 33/60] spapr_iommu: Do not replay mappings from just created DMA window David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 34/60] target/ppc: introduce single fpr_offset() function David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 35/60] target/ppc: introduce single vsrl_offset() function David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 37/60] target/ppc: introduce avr_full_offset() function David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 40/60] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 41/60] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 42/60] mac_newworld: " David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 43/60] ppc/pnv: add a PSI bridge class model David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 44/60] ppc/pnv: add a PSI bridge model for POWER9 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 46/60] ppc/pnv: add a LPC Controller class model David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 48/60] ppc/pnv: add a LPC Controller model for POWER9 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 49/60] ppc/pnv: add SerIRQ routing registers David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 50/60] ppc/pnv: add a OCC model class David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 51/60] ppc/pnv: add a OCC model for POWER9 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 52/60] ppc/pnv: extend XSCOM core support " David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 53/60] ppc/pnv: POWER9 XSCOM quad support David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 54/60] ppc/pnv: activate XSCOM tests for POWER9 David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 55/60] ppc/pnv: add more dummy XSCOM addresses David Gibson
2019-03-10 8:26 ` [Qemu-devel] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 David Gibson
2019-03-10 8:27 ` [Qemu-devel] [PULL 57/60] target/ppc: add HV support for POWER9 David Gibson
[not found] ` <20190312150115.6zuaid43gr7hklt5@unused>
[not found] ` <58de43c6-31d5-a0a3-b443-54a33f11d75a@kaod.org>
[not found] ` <20190312191409.vxnpscrephtk6otv@dhcp-17-165.bos.redhat.com>
[not found] ` <1746025955.7399905.1552419034356.JavaMail.zimbra@redhat.com>
[not found] ` <154364d7-fe5b-4f40-b976-b85ff9060ee0@kaod.org>
2019-06-28 13:20 ` Philippe Mathieu-Daudé
2019-07-01 5:04 ` David Gibson
2019-07-01 9:45 ` Philippe Mathieu-Daudé
2019-07-02 0:14 ` David Gibson
2019-07-02 6:13 ` Cédric Le Goater
2019-07-02 9:22 ` Philippe Mathieu-Daudé
2019-03-10 8:27 ` [Qemu-devel] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64() David Gibson
2019-03-10 8:27 ` [Qemu-devel] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp " David Gibson
2019-03-10 8:27 ` [Qemu-devel] [PULL 60/60] spapr: Use CamelCase properly David Gibson
2019-03-10 9:23 ` [Qemu-devel] [PULL 00/60] ppc-for-4.0 queue 20190310 no-reply
2019-03-10 16:06 ` Peter Maydell
2019-03-11 10:40 ` Alex Bennée
2019-03-12 0:26 ` David Gibson
2019-03-12 0:44 ` David Gibson
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