From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: "Michael S . Tsirkin" <mst@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
qemu-devel@nongnu.org, "Hervé Poussineau" <hpoussin@reactos.org>
Cc: "Eduardo Habkost" <ehabkost@redhat.com>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Aleksandar Rikalo" <arikalo@wavecomp.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [Qemu-devel] [PATCH 4/8] hw/southbridge: Add the PIIX3 chipset to Kconfig
Date: Mon, 11 Mar 2019 00:53:47 +0100 [thread overview]
Message-ID: <20190310235351.1863-5-philmd@redhat.com> (raw)
In-Reply-To: <20190310235351.1863-1-philmd@redhat.com>
The PIIX3 (Intel 82371SB) is a bridge between PCI <-> ISA.
It is an exhanced PIIX, thus contains the same features.
It also contains:
- separate Master/Slave IDE mode
- compliant to PCI rev 2.1 specifications
- IOAPIC
- USB UHCI (2 ports)
- USB Legacy Support (emulated devices):
- 8042 Keyboard Controller
- A20-Gate
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 681e6f1bce..f8494edd67 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,15 @@ config PIIX
#select NMI_PIIX
select ISA_BUS
+config PIIX3
+ bool
+ select PIIX
+ #select PCI_PIIX3
+ #select IDE_PIIX3
+ select IOAPIC
+ select USB_UHCI
+ select I8042
+
config PIIX4
bool
# For historical reasons, SuperIO devices are created in the board
--
2.20.1
next prev parent reply other threads:[~2019-03-10 23:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-10 23:53 [Qemu-devel] [PATCH 0/8] Kconfig: Clean up the PIIX southbridge devices Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 1/8] hw/i2c: The ACPI_SMBUS Kconfig depends on ACPI Philippe Mathieu-Daudé
2019-03-11 0:27 ` Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 2/8] hw/input: Add 8042 PS/2 Keyboard Controller to Kconfig Philippe Mathieu-Daudé
2019-03-11 6:47 ` Thomas Huth
2019-03-11 11:14 ` Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 3/8] hw/southbridge: Add the PIIX chipset " Philippe Mathieu-Daudé
2019-03-10 23:53 ` Philippe Mathieu-Daudé [this message]
2019-03-10 23:53 ` [Qemu-devel] [PATCH 5/8] hw/southbridge: Cleanup the PIIX4 chipset in Kconfig Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 6/8] hw/southbridge: Add ACPI_PIIX4 to Kconfig Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 7/8] hw/i386: The 'isapc' machine is built around a PIIX3 southbridge Philippe Mathieu-Daudé
2019-03-10 23:53 ` [Qemu-devel] [PATCH 8/8] hw/i386: Move ACPI_SMBUS out of I440FX (Kconfig) Philippe Mathieu-Daudé
2019-03-11 3:54 ` [Qemu-devel] [PATCH 0/8] Kconfig: Clean up the PIIX southbridge devices no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190310235351.1863-5-philmd@redhat.com \
--to=philmd@redhat.com \
--cc=amarkovic@wavecomp.com \
--cc=arikalo@wavecomp.com \
--cc=aurelien@aurel32.net \
--cc=ehabkost@redhat.com \
--cc=hpoussin@reactos.org \
--cc=imammedo@redhat.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).