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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@redhat.com>
Date: Mon, 11 Mar 2019 00:53:47 +0100
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Subject: [Qemu-devel] [PATCH 4/8] hw/southbridge: Add the PIIX3 chipset to
 Kconfig
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To: "Michael S . Tsirkin" <mst@redhat.com>, Thomas Huth <thuth@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Igor Mammedov <imammedo@redhat.com>, qemu-devel@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= <hpoussin@reactos.org>
Cc: Eduardo Habkost <ehabkost@redhat.com>, Aleksandar Markovic <amarkovic@wavecomp.com>, Aleksandar Rikalo <arikalo@wavecomp.com>, Aurelien Jarno <aurelien@aurel32.net>, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@redhat.com>

The PIIX3 (Intel 82371SB) is a bridge between PCI <-> ISA.

It is an exhanced PIIX, thus contains the same features.
It also contains:
 - separate Master/Slave IDE mode
 - compliant to PCI rev 2.1 specifications
 - IOAPIC
 - USB UHCI (2 ports)
 - USB Legacy Support (emulated devices):
   - 8042 Keyboard Controller
   - A20-Gate

Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
---
 hw/isa/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 681e6f1bce..f8494edd67 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,15 @@ config PIIX
     #select NMI_PIIX
     select ISA_BUS
=20
+config PIIX3
+    bool
+    select PIIX
+    #select PCI_PIIX3
+    #select IDE_PIIX3
+    select IOAPIC
+    select USB_UHCI
+    select I8042
+
 config PIIX4
     bool
     # For historical reasons, SuperIO devices are created in the board
--=20
2.20.1