[Qemu-devel] [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup

[Qemu-devel] [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup

[Jules Irenge]

This v1 series cleans up all warnings and errors of coding style within cpu.h
file

Jules Irenge (5):
  target/mips: add space to fix checkpatch errors
  target/mips: realign comments to fix checkpatch warnings
  target/mips: replace indentation with space to fix checkpatch errors
  target/mips: remove space to fix checkpatch errors
  target/mips: wrap line into multiple lines to to fix checkpatch errors

 target/mips/cpu.h | 211 +++++++++++++++++++++++++---------------------
 1 file changed, 117 insertions(+), 94 deletions(-)

-- 
2.20.1

[Qemu-devel] [PATCH 1/5] target/mips: add space to fix checkpatch errors

[Jules Irenge]

Add space to fix errors reported by checkpatch.pl tool
"ERROR: spaces required around that ..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that ..."

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a10eeb0de3..2429fe80ac 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
 
 typedef union wr_t wr_t;
 union wr_t {
-    int8_t  b[MSA_WRLEN/8];
-    int16_t h[MSA_WRLEN/16];
-    int32_t w[MSA_WRLEN/32];
-    int64_t d[MSA_WRLEN/64];
+    int8_t  b[MSA_WRLEN / 8];
+    int16_t h[MSA_WRLEN / 16];
+    int32_t w[MSA_WRLEN / 32];
+    int64_t d[MSA_WRLEN / 64];
 };
 
 typedef union fpr_t fpr_t;
@@ -71,16 +71,16 @@ struct CPUMIPSFPUContext {
 #define FCR31_FS 24
 #define FCR31_ABS2008 19
 #define FCR31_NAN2008 18
-#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
-#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
+#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
+#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
-#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
-#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
-#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
-#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
+#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)
+#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)
+#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)
+#define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
 #define FP_INEXACT        1
 #define FP_UNDERFLOW      2
 #define FP_OVERFLOW       4
-- 
2.20.1

Re: [Qemu-devel] [PATCH 1/5] target/mips: add space to fix checkpatch errors

[Aleksandar Markovic]

> From: Jules Irenge <jbi.octave@gmail.com>
> Subject: [PATCH 1/5] target/mips: add space to fix checkpatch errors
> 
> Add space to fix errors reported by checkpatch.pl tool
> "ERROR: spaces required around that ..."
> "ERROR: space required before the open parenthesis"
> "ERROR: space required after that ..."
> 
> Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
> ---
>  target/mips/cpu.h | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
> 

Hello, Jules.

I appreciate this and all other patches in the series.

It looks that here you have additional types of errors
in the same code lines that you change in this patch
("line over 90 characters"), and this causes the script
checkpatch.pl to report errors for this very patch,
which is not allowed.

I think your best option is to blend (squash) existing
patches 1 and 5 onto a single patch.

> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index a10eeb0de3..2429fe80ac 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> 
>  typedef union wr_t wr_t;
>  union wr_t {
> -    int8_t  b[MSA_WRLEN/8];
> -    int16_t h[MSA_WRLEN/16];
> -    int32_t w[MSA_WRLEN/32];
> -    int64_t d[MSA_WRLEN/64];
> +    int8_t  b[MSA_WRLEN / 8];
> +    int16_t h[MSA_WRLEN / 16];
> +    int32_t w[MSA_WRLEN / 32];
> +    int64_t d[MSA_WRLEN / 64];
>  };
> 
>  typedef union fpr_t fpr_t;
> @@ -71,16 +71,16 @@ struct CPUMIPSFPUContext {
>  #define FCR31_FS 24
>  #define FCR31_ABS2008 19
>  #define FCR31_NAN2008 18
> -#define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
> -#define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
> +#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
> +#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)

There is a misalignment here for the last two lines, after
this patch is applied ("do" is misaligned). That should be
corrected.

Thanks a lot!
Aleksandar

>  #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
>  #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
>  #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
>  #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
> -#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
> -#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
> -#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
> -#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
> +#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)
> +#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)
> +#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)
> +#define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
>  #define FP_INEXACT        1
>  #define FP_UNDERFLOW      2
>  #define FP_OVERFLOW       4
> --
> 2.20.1

[Qemu-devel] [PATCH 2/5] target/mips: realign comments to fix checkpatch warnings

[Jules Irenge]

Realign comments to fix warnings issued by checkpatch.pl tool
"WARNING: Block comments use a leading /* on a separate line"
 within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2429fe80ac..bfa595c8a9 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -37,7 +37,8 @@ union fpr_t {
 /* FPU/MSA register mapping is not tested on big-endian hosts. */
     wr_t     wr;   /* vector data */
 };
-/* define FP_ENDIAN_IDX to access the same location
+/*
+ * define FP_ENDIAN_IDX to access the same location
  * in the fpr_t union regardless of the host endianness
  */
 #if defined(HOST_WORDS_BIGENDIAN)
@@ -963,9 +964,11 @@ struct CPUMIPSState {
     /* TMASK defines different execution modes */
 #define MIPS_HFLAG_TMASK  0x1F5807FF
 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
-    /* The KSU flags must be the lowest bits in hflags. The flag order
-       must be the same as defined for CP0 Status. This allows to use
-       the bits as the value of mmu_idx. */
+    /*
+     * The KSU flags must be the lowest bits in hflags. The flag order
+     * must be the same as defined for CP0 Status. This allows to use
+     * the bits as the value of mmu_idx.
+     */
 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
@@ -975,18 +978,22 @@ struct CPUMIPSState {
 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
-    /* True if the MIPS IV COP1X instructions can be used.  This also
-       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
-       and RSQRT.D.  */
+    /*
+     * True if the MIPS IV COP1X instructions can be used.  This also
+     * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
+     * and RSQRT.D.
+     */
 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 #define MIPS_HFLAG_M16_SHIFT 10
-    /* If translation is interrupted between the branch instruction and
+    /*
+     * If translation is interrupted between the branch instruction and
      * the delay slot, record what type of branch it is so that we can
      * resume translation properly.  It might be possible to reduce
-     * this from three bits to two.  */
+     * this from three bits to two.  
+     */
 #define MIPS_HFLAG_BMASK_BASE  0x803800
 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
@@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 
-/* MMU modes definitions. We carefully match the indices with our
-   hflags layout. */
+/*
+ * MMU modes definitions. We carefully match the indices with our
+ * hflags layout.
+ */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _super
 #define MMU_MODE2_SUFFIX _user
@@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 
 #include "exec/cpu-all.h"
 
-/* Memory access type :
+/* 
+ * Memory access type :
  * may be needed for precise access rights control and precise exceptions.
  */
 enum {
-- 
2.20.1

Re: [Qemu-devel] [PATCH 2/5] target/mips: realign comments to fix checkpatch warnings

[Aleksandar Markovic]

> From: Jules Irenge <jbi.octave@gmail.com>
> Subject: [PATCH 2/5] target/mips: realign comments to fix checkpatch warnings
> 
> Realign comments to fix warnings issued by checkpatch.pl tool
> "WARNING: Block comments use a leading /* on a separate line"
>  within "target/mips/cpu.h" file.
> 
> Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
> ---
>  target/mips/cpu.h | 34 ++++++++++++++++++++++------------
>  1 file changed, 22 insertions(+), 12 deletions(-)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 2429fe80ac..bfa595c8a9 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -37,7 +37,8 @@ union fpr_t {
>  /* FPU/MSA register mapping is not tested on big-endian hosts. */
>      wr_t     wr;   /* vector data */
>  };
> -/* define FP_ENDIAN_IDX to access the same location
> +/*
> + * define FP_ENDIAN_IDX to access the same location
>   * in the fpr_t union regardless of the host endianness
>   */
>  #if defined(HOST_WORDS_BIGENDIAN)
> @@ -963,9 +964,11 @@ struct CPUMIPSState {
>      /* TMASK defines different execution modes */
>  #define MIPS_HFLAG_TMASK  0x1F5807FF
>  #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
> -    /* The KSU flags must be the lowest bits in hflags. The flag order
> -       must be the same as defined for CP0 Status. This allows to use
> -       the bits as the value of mmu_idx. */
> +    /*
> +     * The KSU flags must be the lowest bits in hflags. The flag order
> +     * must be the same as defined for CP0 Status. This allows to use
> +     * the bits as the value of mmu_idx.
> +     */
>  #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
>  #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
>  #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
> @@ -975,18 +978,22 @@ struct CPUMIPSState {
>  #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
>  #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
>  #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
> -    /* True if the MIPS IV COP1X instructions can be used.  This also
> -       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
> -       and RSQRT.D.  */
> +    /*
> +     * True if the MIPS IV COP1X instructions can be used.  This also
> +     * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
> +     * and RSQRT.D.
> +     */
>  #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
>  #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
>  #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
>  #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
>  #define MIPS_HFLAG_M16_SHIFT 10
> -    /* If translation is interrupted between the branch instruction and
> +    /*
> +     * If translation is interrupted between the branch instruction and
>       * the delay slot, record what type of branch it is so that we can
>       * resume translation properly.  It might be possible to reduce
> -     * this from three bits to two.  */
> +     * this from three bits to two.  

The last line contains two trailing spaces. Just delete them.

> +     */
>  #define MIPS_HFLAG_BMASK_BASE  0x803800
>  #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
>  #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
> @@ -1073,8 +1080,10 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
>  extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
>  extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
> 
> -/* MMU modes definitions. We carefully match the indices with our
> -   hflags layout. */
> +/*
> + * MMU modes definitions. We carefully match the indices with our
> + * hflags layout.
> + */
>  #define MMU_MODE0_SUFFIX _kernel
>  #define MMU_MODE1_SUFFIX _super
>  #define MMU_MODE2_SUFFIX _user
> @@ -1097,7 +1106,8 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
> 
>  #include "exec/cpu-all.h"
> 
> -/* Memory access type :
> +/* 

The last line contains a trailing space. Just remove it.

> + * Memory access type :
>   * may be needed for precise access rights control and precise exceptions.
>   */
>  enum {
> --
> 2.20.1
> 
> 

Thanks,
Aleksandar

[Qemu-devel] [PATCH 3/5] target/mips: replace indentation with space to fix checkpatch errors

[Jules Irenge]

Replace indentation with space to fix errors issued by checkpatch.pl tool
"ERROR: code indent should never use tabs"
 within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 136 +++++++++++++++++++++++-----------------------
 1 file changed, 68 insertions(+), 68 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index bfa595c8a9..c4278b3ffe 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -96,25 +96,25 @@ struct CPUMIPSFPUContext {
 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 struct CPUMIPSMVPContext {
     int32_t CP0_MVPControl;
-#define CP0MVPCo_CPA	3
-#define CP0MVPCo_STLB	2
-#define CP0MVPCo_VPC	1
-#define CP0MVPCo_EVP	0
+#define CP0MVPCo_CPA     3
+#define CP0MVPCo_STLB    2
+#define CP0MVPCo_VPC     1
+#define CP0MVPCo_EVP     0
     int32_t CP0_MVPConf0;
-#define CP0MVPC0_M	31
-#define CP0MVPC0_TLBS	29
-#define CP0MVPC0_GS	28
-#define CP0MVPC0_PCP	27
-#define CP0MVPC0_PTLBE	16
-#define CP0MVPC0_TCA	15
-#define CP0MVPC0_PVPE	10
-#define CP0MVPC0_PTC	0
+#define CP0MVPC0_M      31
+#define CP0MVPC0_TLBS   29
+#define CP0MVPC0_GS     28
+#define CP0MVPC0_PCP    27
+#define CP0MVPC0_PTLBE  16
+#define CP0MVPC0_TCA    15
+#define CP0MVPC0_PVPE   10
+#define CP0MVPC0_PTC    0
     int32_t CP0_MVPConf1;
-#define CP0MVPC1_CIM	31
-#define CP0MVPC1_CIF	30
-#define CP0MVPC1_PCX	20
-#define CP0MVPC1_PCP2	10
-#define CP0MVPC1_PCP1	0
+#define CP0MVPC1_CIM    31
+#define CP0MVPC1_CIF    30
+#define CP0MVPC1_PCX    20
+#define CP0MVPC1_PCP2   10
+#define CP0MVPC1_PCP1   0
 };
 
 typedef struct mips_def_t mips_def_t;
@@ -482,44 +482,44 @@ struct CPUMIPSState {
  */
     int32_t CP0_Random;
     int32_t CP0_VPEControl;
-#define CP0VPECo_YSI	21
-#define CP0VPECo_GSI	20
-#define CP0VPECo_EXCPT	16
-#define CP0VPECo_TE	15
-#define CP0VPECo_TargTC	0
+#define CP0VPECo_YSI    21
+#define CP0VPECo_GSI    20
+#define CP0VPECo_EXCPT  16
+#define CP0VPECo_TE     15
+#define CP0VPECo_TargTC 0
     int32_t CP0_VPEConf0;
-#define CP0VPEC0_M	31
-#define CP0VPEC0_XTC	21
-#define CP0VPEC0_TCS	19
-#define CP0VPEC0_SCS	18
-#define CP0VPEC0_DSC	17
-#define CP0VPEC0_ICS	16
-#define CP0VPEC0_MVP	1
-#define CP0VPEC0_VPA	0
+#define CP0VPEC0_M      31
+#define CP0VPEC0_XTC    21
+#define CP0VPEC0_TCS    19
+#define CP0VPEC0_SCS    18
+#define CP0VPEC0_DSC    17
+#define CP0VPEC0_ICS    16
+#define CP0VPEC0_MVP    1
+#define CP0VPEC0_VPA    0
     int32_t CP0_VPEConf1;
-#define CP0VPEC1_NCX	20
-#define CP0VPEC1_NCP2	10
-#define CP0VPEC1_NCP1	0
+#define CP0VPEC1_NCX    20
+#define CP0VPEC1_NCP2   10
+#define CP0VPEC1_NCP1   0
     target_ulong CP0_YQMask;
     target_ulong CP0_VPESchedule;
     target_ulong CP0_VPEScheFBack;
     int32_t CP0_VPEOpt;
-#define CP0VPEOpt_IWX7	15
-#define CP0VPEOpt_IWX6	14
-#define CP0VPEOpt_IWX5	13
-#define CP0VPEOpt_IWX4	12
-#define CP0VPEOpt_IWX3	11
-#define CP0VPEOpt_IWX2	10
-#define CP0VPEOpt_IWX1	9
-#define CP0VPEOpt_IWX0	8
-#define CP0VPEOpt_DWX7	7
-#define CP0VPEOpt_DWX6	6
-#define CP0VPEOpt_DWX5	5
-#define CP0VPEOpt_DWX4	4
-#define CP0VPEOpt_DWX3	3
-#define CP0VPEOpt_DWX2	2
-#define CP0VPEOpt_DWX1	1
-#define CP0VPEOpt_DWX0	0
+#define CP0VPEOpt_IWX7  15
+#define CP0VPEOpt_IWX6  14
+#define CP0VPEOpt_IWX5  13
+#define CP0VPEOpt_IWX4  12
+#define CP0VPEOpt_IWX3  11
+#define CP0VPEOpt_IWX2  10
+#define CP0VPEOpt_IWX1  9
+#define CP0VPEOpt_IWX0  8
+#define CP0VPEOpt_DWX7  7
+#define CP0VPEOpt_DWX6  6
+#define CP0VPEOpt_DWX5  5
+#define CP0VPEOpt_DWX4  4
+#define CP0VPEOpt_DWX3  3
+#define CP0VPEOpt_DWX2  2
+#define CP0VPEOpt_DWX1  1
+#define CP0VPEOpt_DWX0  0
 /*
  * CP0 Register 2
  */
@@ -626,33 +626,33 @@ struct CPUMIPSState {
 #define CP0PC_PSN       0     /*  5..0  */
     int32_t CP0_SRSConf0_rw_bitmask;
     int32_t CP0_SRSConf0;
-#define CP0SRSC0_M	31
-#define CP0SRSC0_SRS3	20
-#define CP0SRSC0_SRS2	10
-#define CP0SRSC0_SRS1	0
+#define CP0SRSC0_M     31
+#define CP0SRSC0_SRS3  20
+#define CP0SRSC0_SRS2  10
+#define CP0SRSC0_SRS1  0
     int32_t CP0_SRSConf1_rw_bitmask;
     int32_t CP0_SRSConf1;
-#define CP0SRSC1_M	31
-#define CP0SRSC1_SRS6	20
-#define CP0SRSC1_SRS5	10
-#define CP0SRSC1_SRS4	0
+#define CP0SRSC1_M     31
+#define CP0SRSC1_SRS6  20
+#define CP0SRSC1_SRS5  10
+#define CP0SRSC1_SRS4  0
     int32_t CP0_SRSConf2_rw_bitmask;
     int32_t CP0_SRSConf2;
-#define CP0SRSC2_M	31
-#define CP0SRSC2_SRS9	20
-#define CP0SRSC2_SRS8	10
-#define CP0SRSC2_SRS7	0
+#define CP0SRSC2_M     31
+#define CP0SRSC2_SRS9  20
+#define CP0SRSC2_SRS8  10
+#define CP0SRSC2_SRS7  0
     int32_t CP0_SRSConf3_rw_bitmask;
     int32_t CP0_SRSConf3;
-#define CP0SRSC3_M	31
-#define CP0SRSC3_SRS12	20
-#define CP0SRSC3_SRS11	10
-#define CP0SRSC3_SRS10	0
+#define CP0SRSC3_M     31
+#define CP0SRSC3_SRS12 20
+#define CP0SRSC3_SRS11 10
+#define CP0SRSC3_SRS10 0
     int32_t CP0_SRSConf4_rw_bitmask;
     int32_t CP0_SRSConf4;
-#define CP0SRSC4_SRS15	20
-#define CP0SRSC4_SRS14	10
-#define CP0SRSC4_SRS13	0
+#define CP0SRSC4_SRS15 20
+#define CP0SRSC4_SRS14 10
+#define CP0SRSC4_SRS13 0
 /*
  * CP0 Register 7
  */
-- 
2.20.1

Re: [Qemu-devel] [PATCH 3/5] target/mips: replace indentation with space to fix checkpatch errors

[Aleksandar Markovic]

> From: Jules Irenge <jbi.octave@gmail.com>
> Subject: [PATCH 3/5] target/mips: replace indentation with space to fix checkpatch errors
>
> Replace indentation with space to fix errors issued by checkpatch.pl tool
> "ERROR: code indent should never use tabs"
> within "target/mips/cpu.h" file.
> 
> Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
> ---

This patch is fine.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

[Qemu-devel] [PATCH 4/5] target/mips: remove space to fix checkpatch errors

[Jules Irenge]

Remove space to fix errors issued by checkpatch.pl tool
"ERROR: space prohibited between function name and open parenthesis"
"ERROR: trailing white space"
 within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index c4278b3ffe..238a67c405 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -992,7 +992,7 @@ struct CPUMIPSState {
      * If translation is interrupted between the branch instruction and
      * the delay slot, record what type of branch it is so that we can
      * resume translation properly.  It might be possible to reduce
-     * this from three bits to two.  
+     * this from three bits to two.
      */
 #define MIPS_HFLAG_BMASK_BASE  0x803800
 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
@@ -1072,7 +1072,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
 
 #define ENV_OFFSET offsetof(MIPSCPU, env)
 
-void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
+void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 
 #define cpu_signal_handler cpu_mips_signal_handler
 #define cpu_list mips_cpu_list
@@ -1099,14 +1099,14 @@ static inline int hflags_mmu_index(uint32_t hflags)
     }
 }
 
-static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
+static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
 {
     return hflags_mmu_index(env->hflags);
 }
 
 #include "exec/cpu-all.h"
 
-/* 
+/*
  * Memory access type :
  * may be needed for precise access rights control and precise exceptions.
  */
@@ -1192,7 +1192,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 void itc_reconfigure(struct MIPSITUState *tag);
 
 /* helper.c */
-target_ulong exception_resume_pc (CPUMIPSState *env);
+target_ulong exception_resume_pc(CPUMIPSState *env);
 
 static inline void restore_snan_bit_mode(CPUMIPSState *env)
 {
-- 
2.20.1

[Qemu-devel] [PATCH 5/5] target/mips: wrap line into multiple lines to to fix checkpatch errors

[Jules Irenge]

Wrap line into multiple lines  to fix errors issued by checkpatch.pl tool
ERROR: line over 90 characters"
 within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
---
 target/mips/cpu.h | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 238a67c405..56b0105574 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -72,15 +72,28 @@ struct CPUMIPSFPUContext {
 #define FCR31_FS 24
 #define FCR31_ABS2008 19
 #define FCR31_NAN2008 18
-#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
-#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)
-#define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
+#define SET_FP_COND(num, env)    do { ((env).fcr31) |=  \
+                                        ((num) ? (1 << ((num) + 24)) : \
+                                         (1 << 23)); \
+                                    } while (0)
+#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= \
+                                        ~((num) ? (1 << ((num) + 24)) : \
+                                         (1 << 23)); \
+                                     } while (0)
+#define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | \
+                                  (((env).fcr31 >> 23) & 0x1))
 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
-#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)
-#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)
-#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)
+#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | \
+                                       ((v & 0x3f) << 12); \
+                                     } while (0)
+#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | \
+                                               ((v & 0x1f) << 7);  \
+                                     } while (0)
+#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | \
+                                               ((v & 0x1f) << 2); \
+                                     } while (0)
 #define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
 #define FP_INEXACT        1
 #define FP_UNDERFLOW      2
-- 
2.20.1

Re: [Qemu-devel] [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190403125055.26564-1-jbi.octave@gmail.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190403125055.26564-1-jbi.octave@gmail.com
Subject: [Qemu-devel] [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190319144013.26584-2-pbonzini@redhat.com -> patchew/20190319144013.26584-2-pbonzini@redhat.com
 t [tag update]            patchew/20190401154028.GA10574@erokenlabserver -> patchew/20190401154028.GA10574@erokenlabserver
 * [new tag]               patchew/20190403125055.26564-1-jbi.octave@gmail.com -> patchew/20190403125055.26564-1-jbi.octave@gmail.com
Switched to a new branch 'test'
45a6212b4a target/mips: wrap line into multiple lines to to fix checkpatch errors
71f1867094 target/mips: remove space to fix checkpatch errors
68b4463c72 target/mips: replace indentation with space to fix checkpatch errors
b265859837 target/mips: realign comments to fix checkpatch warnings
fbf61f7591 target/mips: add space to fix checkpatch errors

=== OUTPUT BEGIN ===
1/5 Checking commit fbf61f759167 (target/mips: add space to fix checkpatch errors)
ERROR: line over 90 characters
#40: FILE: target/mips/cpu.h:74:
+#define SET_FP_COND(num, env)    do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)

ERROR: line over 90 characters
#41: FILE: target/mips/cpu.h:75:
+#define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while (0)

ERROR: line over 90 characters
#50: FILE: target/mips/cpu.h:80:
+#define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while (0)

ERROR: line over 90 characters
#51: FILE: target/mips/cpu.h:81:
+#define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while (0)

ERROR: line over 90 characters
#52: FILE: target/mips/cpu.h:82:
+#define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while (0)

total: 5 errors, 0 warnings, 36 lines checked

Patch 1/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/5 Checking commit b265859837f5 (target/mips: realign comments to fix checkpatch warnings)
ERROR: trailing whitespace
#66: FILE: target/mips/cpu.h:995:
+     * this from three bits to two.  $

ERROR: trailing whitespace
#89: FILE: target/mips/cpu.h:1109:
+/* $

total: 2 errors, 0 warnings, 71 lines checked

Patch 2/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/5 Checking commit 68b4463c727f (target/mips: replace indentation with space to fix checkpatch errors)
4/5 Checking commit 71f1867094cf (target/mips: remove space to fix checkpatch errors)
5/5 Checking commit 45a6212b4ad9 (target/mips: wrap line into multiple lines to to fix checkpatch errors)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190403125055.26564-1-jbi.octave@gmail.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [Qemu-devel] [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup

[Aleksandar Markovic]

> From: Jules Irenge <jbi.octave@gmail.com>
> Subject: [PATCH 0/5] target/mips/cpu: errors and warnings coding style cleanup
>
> This v1 series cleans up all warnings and errors of coding style within cpu.h
> file
>

Hi, Jules!

There are a couple of minor problems that I described in my comments
to other patches. Otherwise I like the series.

May I ask you to send v2 of the series, with some needed modifications?

Regards,
Aleksandar

> Jules Irenge (5):
>   target/mips: add space to fix checkpatch errors
>   target/mips: realign comments to fix checkpatch warnings
>   target/mips: replace indentation with space to fix checkpatch errors
>   target/mips: remove space to fix checkpatch errors
>   target/mips: wrap line into multiple lines to to fix checkpatch errors
> 
>  target/mips/cpu.h | 211 +++++++++++++++++++++++++---------------------
>  1 file changed, 117 insertions(+), 94 deletions(-)