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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 2/2] riscv: plic: Log guest errors
Date: Wed,  3 Apr 2019 17:55:23 -0700	[thread overview]
Message-ID: <20190404005523.6513-3-palmer@sifive.com> (raw)
In-Reply-To: <20190404005523.6513-1-palmer@sifive.com>

From: Alistair Francis <Alistair.Francis@wdc.com>

Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/sifive_plic.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 70a85cd07578..7f373d6c9d2c 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
     }
 
 err:
-    error_report("plic: invalid register read: %08x", (uint32_t)addr);
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
     return 0;
 }
 
@@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     } else if (addr >= plic->pending_base && /* 1 bit per source */
                addr < plic->pending_base + (plic->num_sources >> 3))
     {
-        error_report("plic: invalid pending write: %08x", (uint32_t)addr);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid pending write: 0x%" HWADDR_PRIx "",
+                      __func__, addr);
         return;
     } else if (addr >= plic->enable_base && /* 1 bit per source */
         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
@@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
     }
 
 err:
-    error_report("plic: invalid register write: %08x", (uint32_t)addr);
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
 }
 
 static const MemoryRegionOps sifive_plic_ops = {
-- 
2.19.2

  parent reply	other threads:[~2019-04-04  1:00 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-04  0:55 [Qemu-devel] [PULL] RISC-V Patches for 4.0-rc3 Palmer Dabbelt
2019-04-04  0:55 ` [Qemu-devel] [PULL 1/2] riscv: plic: Fix incorrect irq calculation Palmer Dabbelt
2019-04-04  0:55 ` Palmer Dabbelt [this message]
2019-04-04  8:45 ` [Qemu-devel] [PULL] RISC-V Patches for 4.0-rc3 Peter Maydell
2019-04-04 18:18   ` Alistair Francis
2019-04-04 23:29     ` Palmer Dabbelt
2019-04-04 23:29       ` Palmer Dabbelt
  -- strict thread matches above, loose matches on Subject: below --
2019-04-05  0:39 [Qemu-devel] [PULL] RISC-V Patches for 4.0-rc3, v2 Palmer Dabbelt
2019-04-05  0:39 ` [Qemu-devel] [PULL 2/2] riscv: plic: Log guest errors Palmer Dabbelt
2019-04-05  0:39   ` Palmer Dabbelt

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