From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 25/42] target/arm: Add lazy-FP-stacking support to v7m_stack_write()
Date: Mon, 29 Apr 2019 18:00:13 +0100 [thread overview]
Message-ID: <20190429170030.11323-26-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190429170030.11323-1-peter.maydell@linaro.org>
Pushing registers to the stack for v7M needs to handle three cases:
* the "normal" case where we pend exceptions
* an "ignore faults" case where we set FSR bits but
do not pend exceptions (this is used when we are
handling some kinds of derived exception on exception entry)
* a "lazy FP stacking" case, where different FSR bits
are set and the exception is pended differently
Implement this by changing the existing flag argument that
tells us whether to ignore faults or not into an enum that
specifies which of the 3 modes we should handle.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-23-peter.maydell@linaro.org
---
target/arm/helper.c | 118 +++++++++++++++++++++++++++++---------------
1 file changed, 79 insertions(+), 39 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1ed5f1a2513..41531390853 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7575,8 +7575,18 @@ static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
}
}
+/*
+ * What kind of stack write are we doing? This affects how exceptions
+ * generated during the stacking are treated.
+ */
+typedef enum StackingMode {
+ STACK_NORMAL,
+ STACK_IGNFAULTS,
+ STACK_LAZYFP,
+} StackingMode;
+
static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
- ARMMMUIdx mmu_idx, bool ignfault)
+ ARMMMUIdx mmu_idx, StackingMode mode)
{
CPUState *cs = CPU(cpu);
CPUARMState *env = &cpu->env;
@@ -7594,15 +7604,31 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
&attrs, &prot, &page_size, &fi, NULL)) {
/* MPU/SAU lookup failed */
if (fi.type == ARMFault_QEMU_SFault) {
- qemu_log_mask(CPU_LOG_INT,
- "...SecureFault with SFSR.AUVIOL during stacking\n");
- env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
+ if (mode == STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT,
+ "...SecureFault with SFSR.LSPERR "
+ "during lazy stacking\n");
+ env->v7m.sfsr |= R_V7M_SFSR_LSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT,
+ "...SecureFault with SFSR.AUVIOL "
+ "during stacking\n");
+ env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK;
+ }
+ env->v7m.sfsr |= R_V7M_SFSR_SFARVALID_MASK;
env->v7m.sfar = addr;
exc = ARMV7M_EXCP_SECURE;
exc_secure = false;
} else {
- qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKERR\n");
- env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK;
+ if (mode == STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT,
+ "...MemManageFault with CFSR.MLSPERR\n");
+ env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT,
+ "...MemManageFault with CFSR.MSTKERR\n");
+ env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK;
+ }
exc = ARMV7M_EXCP_MEM;
exc_secure = secure;
}
@@ -7612,8 +7638,13 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
attrs, &txres);
if (txres != MEMTX_OK) {
/* BusFault trying to write the data */
- qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n");
- env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK;
+ if (mode == STACK_LAZYFP) {
+ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n");
+ env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK;
+ } else {
+ qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n");
+ env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK;
+ }
exc = ARMV7M_EXCP_BUS;
exc_secure = false;
goto pend_fault;
@@ -7628,11 +7659,19 @@ pend_fault:
* later if we have two derived exceptions.
* The only case when we must not pend the exception but instead
* throw it away is if we are doing the push of the callee registers
- * and we've already generated a derived exception. Even in this
- * case we will still update the fault status registers.
+ * and we've already generated a derived exception (this is indicated
+ * by the caller passing STACK_IGNFAULTS). Even in this case we will
+ * still update the fault status registers.
*/
- if (!ignfault) {
+ switch (mode) {
+ case STACK_NORMAL:
armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure);
+ break;
+ case STACK_LAZYFP:
+ armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure);
+ break;
+ case STACK_IGNFAULTS:
+ break;
}
return false;
}
@@ -8009,6 +8048,7 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
uint32_t limit;
bool want_psp;
uint32_t sig;
+ StackingMode smode = ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL;
if (dotailchain) {
bool mode = lr & R_V7M_EXCRET_MODE_MASK;
@@ -8052,23 +8092,15 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
*/
sig = v7m_integrity_sig(env, lr);
stacked_ok =
- v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx,
- ignore_faults) &&
- v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx,
- ignore_faults);
+ v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smode) &&
+ v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smode);
/* Update SP regardless of whether any of the stack accesses failed. */
*frame_sp_p = frameptr;
@@ -8347,14 +8379,20 @@ static bool v7m_push_stack(ARMCPU *cpu)
* if it has higher priority).
*/
stacked_ok = stacked_ok &&
- v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) &&
- v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false);
+ v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 4, env->regs[1],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 8, env->regs[2],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 12, env->regs[3],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 16, env->regs[12],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 20, env->regs[14],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 24, env->regs[15],
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL);
if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) {
/* FPU is active, try to save its registers */
@@ -8404,12 +8442,14 @@ static bool v7m_push_stack(ARMCPU *cpu)
faddr += 8; /* skip the slot for the FPSCR */
}
stacked_ok = stacked_ok &&
- v7m_stack_write(cpu, faddr, slo, mmu_idx, false) &&
- v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, false);
+ v7m_stack_write(cpu, faddr, slo,
+ mmu_idx, STACK_NORMAL) &&
+ v7m_stack_write(cpu, faddr + 4, shi,
+ mmu_idx, STACK_NORMAL);
}
stacked_ok = stacked_ok &&
v7m_stack_write(cpu, frameptr + 0x60,
- vfp_get_fpscr(env), mmu_idx, false);
+ vfp_get_fpscr(env), mmu_idx, STACK_NORMAL);
if (cpacr_pass) {
for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) {
*aa32_vfp_dreg(env, i / 2) = 0;
--
2.20.1
next prev parent reply other threads:[~2019-04-29 17:02 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-29 16:59 [Qemu-devel] [PULL 00/42] target-arm queue Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 01/42] hw/arm/smmuv3: Remove SMMUNotifierNode Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 02/42] hw/ssi/xilinx_spips: Avoid variable length array Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 03/42] configure: Remove --source-path option Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 04/42] target/arm: Make sure M-profile FPSCR RES0 bits are not settable Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 06/42] target/arm: Implement dummy versions of M-profile FP-related registers Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-profile Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 08/42] target/arm: Honour M-profile FP enable bits Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 10/42] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 16:59 ` [Qemu-devel] [PULL 11/42] target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL Peter Maydell
2019-04-29 16:59 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 12/42] target/arm/helper: don't return early for STKOF faults during stacking Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 13/42] target/arm: Handle floating point registers in exception entry Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 14/42] target/arm: Implement v7m_update_fpccr() Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 16/42] target/arm: Clean excReturn bits when tail chaining Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 17/42] target/arm: Allow for floating point in callee stack integrity check Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 18/42] target/arm: Handle floating point registers in exception return Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 19/42] target/arm: Move NS TBFLAG from bit 19 to bit 6 Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 20/42] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing M-profile floating point insns Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 23/42] target/arm: New helper function arm_v7m_mmu_idx_all() Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 24/42] target/arm: New function armv7m_nvic_set_pending_lazyfp() Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` Peter Maydell [this message]
2019-04-29 17:00 ` [Qemu-devel] [PULL 25/42] target/arm: Add lazy-FP-stacking support to v7m_stack_write() Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 26/42] target/arm: Implement M-profile lazy FP state preservation Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 27/42] target/arm: Implement VLSTM for v7M CPUs with an FPU Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 28/42] target/arm: Implement VLLDM " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 29/42] target/arm: Enable FPU for Cortex-M4 and Cortex-M33 Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 30/42] hw/dma: Compile the bcm2835_dma device as common object Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 31/42] hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 32/42] hw/arm/nseries: Use TYPE_TMP105 " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 33/42] hw/display/tc6393xb: Remove unused functions Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 34/42] hw/devices: Move TC6393XB declarations into a new header Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 35/42] hw/devices: Move Blizzard " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 36/42] hw/devices: Move CBus " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 37/42] hw/devices: Move Gamepad " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 38/42] hw/devices: Move TI touchscreen " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 39/42] hw/devices: Move LAN9118 " Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 40/42] hw/net/ne2000-isa: Add guards to the header Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 41/42] hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 17:00 ` [Qemu-devel] [PULL 42/42] hw/devices: Move SMSC 91C111 declaration into a new header Peter Maydell
2019-04-29 17:00 ` Peter Maydell
2019-04-29 18:10 ` [Qemu-devel] [PULL 00/42] target-arm queue Peter Maydell
2019-04-29 18:10 ` Peter Maydell
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