From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 09/29] tcg: Manually expand INDEX_op_dup_vec
Date: Tue, 30 Apr 2019 22:05:16 -0700 [thread overview]
Message-ID: <20190501050536.15580-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190501050536.15580-1-richard.henderson@linaro.org>
This case is similar to INDEX_op_mov_* in that we need to do
different things depending on the current location of the source.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.inc.c | 9 ++--
tcg/i386/tcg-target.inc.c | 8 ++-
tcg/tcg.c | 102 +++++++++++++++++++++++++++++++++++
3 files changed, 109 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index e443b5df23..3cefdd1e43 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2108,10 +2108,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
- case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
g_assert_not_reached();
@@ -2208,9 +2206,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_not_vec:
tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
break;
- case INDEX_op_dup_vec:
- tcg_out_dup_vec(s, type, vece, a0, a1);
- break;
case INDEX_op_shli_vec:
tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
break;
@@ -2254,6 +2249,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
}
break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 0d621670c7..3c8229d413 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2603,10 +2603,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
- case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2795,9 +2793,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st_vec:
tcg_out_st(s, type, a0, a1, a2);
break;
- case INDEX_op_dup_vec:
- tcg_out_dup_vec(s, type, vece, a0, a1);
- break;
case INDEX_op_x86_shufps_vec:
insn = OPC_SHUFPS;
@@ -2839,6 +2834,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out8(s, a2);
break;
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 3ef4d3478d..78fd0e4594 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3407,6 +3407,105 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
}
}
+static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
+{
+ const TCGLifeData arg_life = op->life;
+ TCGRegSet dup_out_regs, dup_in_regs;
+ TCGTemp *its, *ots;
+ TCGType itype, vtype;
+ unsigned vece;
+ bool ok;
+
+ ots = arg_temp(op->args[0]);
+ its = arg_temp(op->args[1]);
+
+ /* There should be no fixed vector registers. */
+ tcg_debug_assert(!ots->fixed_reg);
+
+ itype = its->type;
+ vece = TCGOP_VECE(op);
+ vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
+
+ if (its->val_type == TEMP_VAL_CONST) {
+ /* Propagate constant via movi -> dupi. */
+ tcg_target_ulong val = its->val;
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, its);
+ }
+ tcg_reg_alloc_do_movi(s, ots, val, arg_life, op->output_pref[0]);
+ return;
+ }
+
+ dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
+ dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+
+ /* Allocate the output register now. */
+ if (ots->val_type != TEMP_VAL_REG) {
+ TCGRegSet allocated_regs = s->reserved_regs;
+
+ if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) {
+ /* Make sure to not spill the input register. */
+ tcg_regset_set_reg(allocated_regs, its->reg);
+ }
+ ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
+ op->output_pref[0], ots->indirect_base);
+ ots->val_type = TEMP_VAL_REG;
+ ots->mem_coherent = 0;
+ s->reg_to_temp[ots->reg] = ots;
+ }
+
+ switch (its->val_type) {
+ case TEMP_VAL_REG:
+ /*
+ * The dup constriaints must be broad, covering all possible VECE.
+ * However, tcg_op_dup_vec() gets to see the VECE and we allow it
+ * to fail, indicating that extra moves are required for that case.
+ */
+ if (tcg_regset_test_reg(dup_in_regs, its->reg)) {
+ if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) {
+ goto done;
+ }
+ /* Try again from memory or a vector input register. */
+ }
+ if (!its->mem_coherent) {
+ /*
+ * The input register is not synced, and so an extra store
+ * would be required to use memory. Attempt an integer-vector
+ * register move first. We do not have a TCGRegSet for this.
+ */
+ if (tcg_out_mov(s, itype, ots->reg, its->reg)) {
+ break;
+ }
+ /* Sync the temp back to its slot and load from there. */
+ temp_sync(s, its, s->reserved_regs, 0, 0);
+ }
+ /* fall through */
+
+ case TEMP_VAL_MEM:
+ /* TODO: dup from memory */
+ tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ /* We now have a vector input register, so dup must succeed. */
+ ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg);
+ tcg_debug_assert(ok);
+
+ done:
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, its);
+ }
+ if (NEED_SYNC_ARG(0)) {
+ temp_sync(s, ots, s->reserved_regs, 0, 0);
+ }
+ if (IS_DEAD_ARG(0)) {
+ temp_dead(s, ots);
+ }
+}
+
static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
{
const TCGLifeData arg_life = op->life;
@@ -3981,6 +4080,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
case INDEX_op_dupi_vec:
tcg_reg_alloc_movi(s, op);
break;
+ case INDEX_op_dup_vec:
+ tcg_reg_alloc_dup(s, op);
+ break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
size_t off = tcg_current_code_size(s);
--
2.17.1
next prev parent reply other threads:[~2019-05-01 5:06 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 5:05 [Qemu-devel] [PATCH v2 00/29] tcg vector improvements Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 01/29] tcg: Implement tcg_gen_gvec_3i() Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 15:23 ` Alex Bennée
2019-05-01 15:23 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 02/29] tcg: Do not recreate INDEX_op_neg_vec unless supported Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 15:26 ` Alex Bennée
2019-05-01 15:26 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 03/29] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 15:56 ` Alex Bennée
2019-05-01 15:56 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 04/29] tcg: Specify optional vector requirements with a list Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 17:24 ` Alex Bennée
2019-05-01 17:24 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 05/29] tcg: Assert fixed_reg is read-only Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 17:26 ` Alex Bennée
2019-05-01 17:26 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 06/29] tcg: Return bool success from tcg_out_mov Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 17:29 ` Alex Bennée
2019-05-01 17:29 ` Alex Bennée
2019-05-01 20:31 ` Richard Henderson
2019-05-01 20:31 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 07/29] tcg: Support cross-class moves without instruction support Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 17:34 ` Alex Bennée
2019-05-01 17:34 ` Alex Bennée
2019-05-01 20:18 ` Richard Henderson
2019-05-01 20:18 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 08/29] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 17:37 ` Alex Bennée
2019-05-01 17:37 ` Alex Bennée
2019-05-01 20:21 ` Richard Henderson
2019-05-01 20:21 ` Richard Henderson
2019-05-01 5:05 ` Richard Henderson [this message]
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 09/29] tcg: Manually expand INDEX_op_dup_vec Richard Henderson
2019-05-02 9:42 ` Alex Bennée
2019-05-02 9:42 ` Alex Bennée
2019-05-02 15:24 ` Richard Henderson
2019-05-02 15:24 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 10/29] tcg: Add tcg_out_dupm_vec to the backend interface Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 11/29] tcg/i386: Implement tcg_out_dupm_vec Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 12/29] tcg/aarch64: " Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 13:26 ` Alex Bennée
2019-05-02 13:26 ` Alex Bennée
2019-05-02 15:35 ` Richard Henderson
2019-05-02 15:35 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 13/29] tcg: Add INDEX_op_dup_mem_vec Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 13:30 ` Alex Bennée
2019-05-02 13:30 ` Alex Bennée
2019-05-02 15:38 ` Richard Henderson
2019-05-02 15:38 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 14/29] tcg: Add gvec expanders for variable shift Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 14:08 ` Alex Bennée
2019-05-02 14:08 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 15/29] tcg/i386: Support vector variable shift opcodes Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 16/29] tcg/aarch64: " Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 14:12 ` Alex Bennée
2019-05-02 14:12 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 17/29] tcg: Add gvec expanders for vector shift by scalar Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 14:37 ` Alex Bennée
2019-05-02 14:37 ` Alex Bennée
2019-05-02 15:46 ` Richard Henderson
2019-05-02 15:46 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 18/29] tcg/i386: Support vector scalar shift opcodes Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 19/29] tcg: Add support for integer absolute value Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 15:25 ` Alex Bennée
2019-05-02 15:25 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 20/29] tcg: Add support for vector " Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 15:47 ` Alex Bennée
2019-05-02 15:47 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 21/29] tcg/i386: Support " Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 22/29] tcg/aarch64: " Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 15:49 ` Alex Bennée
2019-05-02 15:49 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 23/29] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 16:07 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2019-05-02 16:07 ` Alex Bennée
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 24/29] target/cris: Use tcg_gen_abs_tl Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 25/29] target/ppc: Use tcg_gen_abs_i32 Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 26/29] target/ppc: Use tcg_gen_abs_tl Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 27/29] target/s390x: Use tcg_gen_abs_i64 Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-02 13:44 ` David Hildenbrand
2019-05-02 13:44 ` David Hildenbrand
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 28/29] target/tricore: Use tcg_gen_abs_tl Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 5:05 ` [Qemu-devel] [PATCH v2 29/29] target/xtensa: Use tcg_gen_abs_i32 Richard Henderson
2019-05-01 5:05 ` Richard Henderson
2019-05-01 15:15 ` Max Filippov
2019-05-01 15:15 ` Max Filippov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190501050536.15580-10-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).