From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:38266) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMCPy-0007rU-Ox for qemu-devel@nongnu.org; Thu, 02 May 2019 10:10:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMCPx-0005y3-Mi for qemu-devel@nongnu.org; Thu, 02 May 2019 10:10:34 -0400 From: David Hildenbrand Date: Thu, 2 May 2019 16:09:42 +0200 Message-Id: <20190502141019.6385-4-david@redhat.com> In-Reply-To: <20190502141019.6385-1-david@redhat.com> References: <20190502141019.6385-1-david@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 03/40] s390x/tcg: Implement VECTOR ADD WITH CARRY List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Thomas Huth , Cornelia Huck , Richard Henderson , David Hildenbrand , Richard Henderson Only slightly ugly, perform two additions. At least it is only supported for 128 bit elements. Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64(). Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.inc.c | 63 +++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index f0e62b9aa8..38d1e22a6d 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1060,6 +1060,8 @@ F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC) /* VECTOR ADD COMPUTE CARRY */ F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC) +/* VECTOR ADD WITH CARRY */ + F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC) =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.= inc.c index 312c5f67be..c70f380209 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -196,6 +196,41 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn f= n, uint8_t d, uint8_t a, tcg_temp_free_i64(bl); } =20 +typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 = al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 = bh, + TCGv_i64 cl, TCGv_i64 ch); +static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_= t a, + uint8_t b, uint8_t c) +{ + TCGv_i64 dh =3D tcg_temp_new_i64(); + TCGv_i64 dl =3D tcg_temp_new_i64(); + TCGv_i64 ah =3D tcg_temp_new_i64(); + TCGv_i64 al =3D tcg_temp_new_i64(); + TCGv_i64 bh =3D tcg_temp_new_i64(); + TCGv_i64 bl =3D tcg_temp_new_i64(); + TCGv_i64 ch =3D tcg_temp_new_i64(); + TCGv_i64 cl =3D tcg_temp_new_i64(); + + read_vec_element_i64(ah, a, 0, ES_64); + read_vec_element_i64(al, a, 1, ES_64); + read_vec_element_i64(bh, b, 0, ES_64); + read_vec_element_i64(bl, b, 1, ES_64); + read_vec_element_i64(ch, c, 0, ES_64); + read_vec_element_i64(cl, c, 1, ES_64); + fn(dl, dh, al, ah, bl, bh, cl, ch); + write_vec_element_i64(dh, d, 0, ES_64); + write_vec_element_i64(dl, d, 1, ES_64); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(dl); + tcg_temp_free_i64(ah); + tcg_temp_free_i64(al); + tcg_temp_free_i64(bh); + tcg_temp_free_i64(bl); + tcg_temp_free_i64(ch); + tcg_temp_free_i64(cl); +} + static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c) { switch (es) { @@ -1079,3 +1114,31 @@ static DisasJumpType op_vacc(DisasContext *s, Disa= sOps *o) get_field(s->fields, v3), &g[es]); return DISAS_NEXT; } + +static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 = ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 = ch) +{ + TCGv_i64 tl =3D tcg_temp_new_i64(); + TCGv_i64 th =3D tcg_const_i64(0); + + /* extract the carry only */ + tcg_gen_extract_i64(tl, cl, 0, 1); + tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); +} + +static DisasJumpType op_vac(DisasContext *s, DisasOps *o) +{ + if (get_field(s->fields, m5) !=3D ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_ac2_i64, get_field(s->fields, v1), + get_field(s->fields, v2), get_field(s->fields, v3)= , + get_field(s->fields, v4)); + return DISAS_NEXT; +} --=20 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E894C43219 for ; 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Thu, 02 May 2019 10:10:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59984) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hMCPx-0005xX-F1; Thu, 02 May 2019 10:10:33 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B3E44C060209; Thu, 2 May 2019 14:10:32 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-88.ams2.redhat.com [10.36.117.88]) by smtp.corp.redhat.com (Postfix) with ESMTP id 337BE7BA2E; Thu, 2 May 2019 14:10:31 +0000 (UTC) From: David Hildenbrand To: qemu-devel@nongnu.org Date: Thu, 2 May 2019 16:09:42 +0200 Message-Id: <20190502141019.6385-4-david@redhat.com> In-Reply-To: <20190502141019.6385-1-david@redhat.com> References: <20190502141019.6385-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 02 May 2019 14:10:32 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 03/40] s390x/tcg: Implement VECTOR ADD WITH CARRY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , David Hildenbrand , Cornelia Huck , Richard Henderson , qemu-s390x@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="UTF-8" Message-ID: <20190502140942.XOG70NecbeGgXHWKJvfv4nc1ja5aLfz0tb9tFNIx588@z> Only slightly ugly, perform two additions. At least it is only supported for 128 bit elements. Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64(). Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 2 ++ target/s390x/translate_vx.inc.c | 63 +++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index f0e62b9aa8..38d1e22a6d 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1060,6 +1060,8 @@ F(0xe7f3, VA, VRR_c, V, 0, 0, 0, 0, va, 0, IF_VEC) /* VECTOR ADD COMPUTE CARRY */ F(0xe7f1, VACC, VRR_c, V, 0, 0, 0, 0, vacc, 0, IF_VEC) +/* VECTOR ADD WITH CARRY */ + F(0xe7bb, VAC, VRR_d, V, 0, 0, 0, 0, vac, 0, IF_VEC) =20 #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.= inc.c index 312c5f67be..c70f380209 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -196,6 +196,41 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn f= n, uint8_t d, uint8_t a, tcg_temp_free_i64(bl); } =20 +typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 = al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 = bh, + TCGv_i64 cl, TCGv_i64 ch); +static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_= t a, + uint8_t b, uint8_t c) +{ + TCGv_i64 dh =3D tcg_temp_new_i64(); + TCGv_i64 dl =3D tcg_temp_new_i64(); + TCGv_i64 ah =3D tcg_temp_new_i64(); + TCGv_i64 al =3D tcg_temp_new_i64(); + TCGv_i64 bh =3D tcg_temp_new_i64(); + TCGv_i64 bl =3D tcg_temp_new_i64(); + TCGv_i64 ch =3D tcg_temp_new_i64(); + TCGv_i64 cl =3D tcg_temp_new_i64(); + + read_vec_element_i64(ah, a, 0, ES_64); + read_vec_element_i64(al, a, 1, ES_64); + read_vec_element_i64(bh, b, 0, ES_64); + read_vec_element_i64(bl, b, 1, ES_64); + read_vec_element_i64(ch, c, 0, ES_64); + read_vec_element_i64(cl, c, 1, ES_64); + fn(dl, dh, al, ah, bl, bh, cl, ch); + write_vec_element_i64(dh, d, 0, ES_64); + write_vec_element_i64(dl, d, 1, ES_64); + + tcg_temp_free_i64(dh); + tcg_temp_free_i64(dl); + tcg_temp_free_i64(ah); + tcg_temp_free_i64(al); + tcg_temp_free_i64(bh); + tcg_temp_free_i64(bl); + tcg_temp_free_i64(ch); + tcg_temp_free_i64(cl); +} + static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c) { switch (es) { @@ -1079,3 +1114,31 @@ static DisasJumpType op_vacc(DisasContext *s, Disa= sOps *o) get_field(s->fields, v3), &g[es]); return DISAS_NEXT; } + +static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 = ah, + TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 = ch) +{ + TCGv_i64 tl =3D tcg_temp_new_i64(); + TCGv_i64 th =3D tcg_const_i64(0); + + /* extract the carry only */ + tcg_gen_extract_i64(tl, cl, 0, 1); + tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + + tcg_temp_free_i64(tl); + tcg_temp_free_i64(th); +} + +static DisasJumpType op_vac(DisasContext *s, DisasOps *o) +{ + if (get_field(s->fields, m5) !=3D ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_gvec128_4_i64(gen_ac2_i64, get_field(s->fields, v1), + get_field(s->fields, v2), get_field(s->fields, v3)= , + get_field(s->fields, v4)); + return DISAS_NEXT; +} --=20 2.20.1