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From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, Thomas Huth <thuth@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Richard Henderson <rth@twiddle.net>,
	David Hildenbrand <david@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK
Date: Thu,  2 May 2019 16:10:19 +0200	[thread overview]
Message-ID: <20190502141019.6385-41-david@redhat.com> (raw)
In-Reply-To: <20190502141019.6385-1-david@redhat.com>

Let's return the cc value directly via cpu_env. Unfortunately there
isn't a simple way to calculate the value lazily - one would have to
calculate and store e.g. the population count of the mask and the
result so it can be evaluated in a cc helper.

But as VTM only sets the cc, we can assume the value will be needed soon
either way.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/helper.h           |  1 +
 target/s390x/insn-data.def      |  2 ++
 target/s390x/translate_vx.inc.c | 11 +++++++++++
 target/s390x/vec_int_helper.c   | 18 ++++++++++++++++++
 4 files changed, 32 insertions(+)

diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 2cb1f369bd..7755a96c33 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -209,6 +209,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
 DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
 DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
 
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a52db41388..e61475bdc4 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1188,6 +1188,8 @@
     F(0xe767, VSUMQ,   VRR_c, V,   0, 0, 0, 0, vsumq, 0, IF_VEC)
 /* VECTOR SUM ACROSS WORD */
     F(0xe764, VSUM,    VRR_c, V,   0, 0, 0, 0, vsum, 0, IF_VEC)
+/* VECTOR TEST UNDER MASK */
+    F(0xe7d8, VTM,     VRR_a, V,   0, 0, 0, 0, vtm, 0, IF_VEC)
 
 #ifndef CONFIG_USER_ONLY
 /* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 23eca2b332..e12ba00a13 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
 #define gen_gvec_2i_ool(v1, v2, c, data, fn) \
     tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                         c, 16, 16, data, fn)
+#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
+    tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+                       ptr, 16, 16, data, fn)
 #define gen_gvec_3(v1, v2, v3, gen) \
     tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                    vec_full_reg_offset(v3), 16, 16, gen)
@@ -2338,3 +2341,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
     tcg_temp_free_i32(tmp);
     return DISAS_NEXT;
 }
+
+static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
+{
+    gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+                   cpu_env, 0, gen_helper_gvec_vtm);
+    set_cc_static(s);
+    return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 09137dab99..3e8837e09a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -583,3 +583,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3,        \
 }
 DEF_VSCBI(8)
 DEF_VSCBI(16)
+
+void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
+                      uint32_t desc)
+{
+    S390Vector tmp;
+
+    s390_vec_and(&tmp, v1, v2);
+    if (s390_vec_is_zero(&tmp)) {
+        /* Selected bits all zeros; or all mask bits zero */
+        env->cc_op = 0;
+    } else if (s390_vec_equal(&tmp, v2)) {
+        /* Selected bits all ones */
+        env->cc_op = 3;
+    } else {
+        /* Selected bits a mix of zeros and ones */
+        env->cc_op = 1;
+    }
+}
-- 
2.20.1

WARNING: multiple messages have this Message-ID (diff)
From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: Thomas Huth <thuth@redhat.com>,
	David Hildenbrand <david@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK
Date: Thu,  2 May 2019 16:10:19 +0200	[thread overview]
Message-ID: <20190502141019.6385-41-david@redhat.com> (raw)
Message-ID: <20190502141019.AlaY7qkqph94RYhDE2xw2ulxPjcMUgDbM2QM9Eo-z6s@z> (raw)
In-Reply-To: <20190502141019.6385-1-david@redhat.com>

Let's return the cc value directly via cpu_env. Unfortunately there
isn't a simple way to calculate the value lazily - one would have to
calculate and store e.g. the population count of the mask and the
result so it can be evaluated in a cc helper.

But as VTM only sets the cc, we can assume the value will be needed soon
either way.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/helper.h           |  1 +
 target/s390x/insn-data.def      |  2 ++
 target/s390x/translate_vx.inc.c | 11 +++++++++++
 target/s390x/vec_int_helper.c   | 18 ++++++++++++++++++
 4 files changed, 32 insertions(+)

diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 2cb1f369bd..7755a96c33 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -209,6 +209,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
 DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
 DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
 DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
+DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
 
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index a52db41388..e61475bdc4 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1188,6 +1188,8 @@
     F(0xe767, VSUMQ,   VRR_c, V,   0, 0, 0, 0, vsumq, 0, IF_VEC)
 /* VECTOR SUM ACROSS WORD */
     F(0xe764, VSUM,    VRR_c, V,   0, 0, 0, 0, vsum, 0, IF_VEC)
+/* VECTOR TEST UNDER MASK */
+    F(0xe7d8, VTM,     VRR_a, V,   0, 0, 0, 0, vtm, 0, IF_VEC)
 
 #ifndef CONFIG_USER_ONLY
 /* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 23eca2b332..e12ba00a13 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
 #define gen_gvec_2i_ool(v1, v2, c, data, fn) \
     tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                         c, 16, 16, data, fn)
+#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
+    tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
+                       ptr, 16, 16, data, fn)
 #define gen_gvec_3(v1, v2, v3, gen) \
     tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                    vec_full_reg_offset(v3), 16, 16, gen)
@@ -2338,3 +2341,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
     tcg_temp_free_i32(tmp);
     return DISAS_NEXT;
 }
+
+static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
+{
+    gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+                   cpu_env, 0, gen_helper_gvec_vtm);
+    set_cc_static(s);
+    return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_int_helper.c b/target/s390x/vec_int_helper.c
index 09137dab99..3e8837e09a 100644
--- a/target/s390x/vec_int_helper.c
+++ b/target/s390x/vec_int_helper.c
@@ -583,3 +583,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3,        \
 }
 DEF_VSCBI(8)
 DEF_VSCBI(16)
+
+void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
+                      uint32_t desc)
+{
+    S390Vector tmp;
+
+    s390_vec_and(&tmp, v1, v2);
+    if (s390_vec_is_zero(&tmp)) {
+        /* Selected bits all zeros; or all mask bits zero */
+        env->cc_op = 0;
+    } else if (s390_vec_equal(&tmp, v2)) {
+        /* Selected bits all ones */
+        env->cc_op = 3;
+    } else {
+        /* Selected bits a mix of zeros and ones */
+        env->cc_op = 1;
+    }
+}
-- 
2.20.1



  parent reply	other threads:[~2019-05-02 14:12 UTC|newest]

Thread overview: 99+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-02 14:09 [Qemu-devel] [PATCH v3 00/40] s390x/tcg: Vector Instruction Support Part 2 David Hildenbrand
2019-05-02 14:09 ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 01/40] s390x/tcg: Implement VECTOR ADD David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 02/40] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-03  3:45   ` Richard Henderson
2019-05-03  3:45     ` Richard Henderson
2019-05-03 12:46     ` David Hildenbrand
2019-05-03 12:46       ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 03/40] s390x/tcg: Implement VECTOR ADD WITH CARRY David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 04/40] s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRY David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-03  3:46   ` Richard Henderson
2019-05-03  3:46     ` Richard Henderson
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 05/40] s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT) David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 06/40] s390x/tcg: Implement VECTOR AVERAGE David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 07/40] s390x/tcg: Implement VECTOR AVERAGE LOGICAL David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 08/40] s390x/tcg: Implement VECTOR CHECKSUM David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 09/40] s390x/tcg: Implement VECTOR ELEMENT COMPARE * David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 10/40] s390x/tcg: Implement VECTOR " David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 11/40] s390x/tcg: Implement VECTOR COUNT LEADING ZEROS David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 12/40] s390x/tcg: Implement VECTOR COUNT TRAILING ZEROS David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-03  5:18   ` Richard Henderson
2019-05-03  5:18     ` Richard Henderson
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 13/40] s390x/tcg: Implement VECTOR EXCLUSIVE OR David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 14/40] s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE) David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 15/40] s390x/tcg: Implement VECTOR LOAD COMPLEMENT David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 16/40] s390x/tcg: Implement VECTOR LOAD POSITIVE David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 17/40] s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL) David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 18/40] s390x/tcg: Implement VECTOR MULTIPLY AND ADD * David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 19/40] s390x/tcg: Implement VECTOR MULTIPLY * David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:09 ` [Qemu-devel] [PATCH v3 20/40] s390x/tcg: Implement VECTOR NAND David Hildenbrand
2019-05-02 14:09   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 21/40] s390x/tcg: Implement VECTOR NOR David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 22/40] s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 23/40] s390x/tcg: Implement VECTOR OR David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 24/40] s390x/tcg: Implement VECTOR OR WITH COMPLEMENT David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 25/40] s390x/tcg: Implement VECTOR POPULATION COUNT David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 26/40] s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 27/40] s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-03  5:25   ` Richard Henderson
2019-05-03  5:25     ` Richard Henderson
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 28/40] s390x/tcg: Implement VECTOR ELEMENT SHIFT David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 29/40] s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 30/40] s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-03  5:56   ` Richard Henderson
2019-05-03  5:56     ` Richard Henderson
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 31/40] s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 32/40] s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 33/40] s390x/tcg: Implement VECTOR SUBTRACT David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 34/40] s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-03  5:57   ` Richard Henderson
2019-05-03  5:57     ` Richard Henderson
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 35/40] s390x/tcg: Implement VECTOR SUBTRACT WITH " David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 36/40] s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE " David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-03 18:25   ` Richard Henderson
2019-05-03 18:25     ` Richard Henderson
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 37/40] s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 38/40] s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` [Qemu-devel] [PATCH v3 39/40] s390x/tcg: Implement VECTOR SUM ACROSS WORD David Hildenbrand
2019-05-02 14:10   ` David Hildenbrand
2019-05-02 14:10 ` David Hildenbrand [this message]
2019-05-02 14:10   ` [Qemu-devel] [PATCH v3 40/40] s390x/tcg: Implement VECTOR TEST UNDER MASK David Hildenbrand
2019-05-06  9:42   ` David Hildenbrand

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