From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, david@redhat.com,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl
Date: Fri, 3 May 2019 22:52:58 -0700 [thread overview]
Message-ID: <20190504055300.18426-30-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20190423102145.14812-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8f6416144e..06c4485e55 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void gen_abs(TCGv ret, TCGv r1)
{
- TCGv temp = tcg_temp_new();
- TCGv t0 = tcg_const_i32(0);
-
- tcg_gen_neg_tl(temp, r1);
- tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
+ tcg_gen_abs_tl(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
@@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1)
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
-
- tcg_temp_free(temp);
- tcg_temp_free(t0);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
@@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
@@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
david@redhat.com
Subject: [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl
Date: Fri, 3 May 2019 22:52:58 -0700 [thread overview]
Message-ID: <20190504055300.18426-30-richard.henderson@linaro.org> (raw)
Message-ID: <20190504055258.0zMAueOdluIWOSw8T7cEEoYGYFEQwx6fPDgR5cIJsGE@z> (raw)
In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20190423102145.14812-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 27 +++++----------------------
1 file changed, 5 insertions(+), 22 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 8f6416144e..06c4485e55 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2415,11 +2415,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
static inline void gen_abs(TCGv ret, TCGv r1)
{
- TCGv temp = tcg_temp_new();
- TCGv t0 = tcg_const_i32(0);
-
- tcg_gen_neg_tl(temp, r1);
- tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
+ tcg_gen_abs_tl(ret, r1);
/* overflow can only happen, if r1 = 0x80000000 */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
@@ -2430,9 +2426,6 @@ static inline void gen_abs(TCGv ret, TCGv r1)
tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
/* calc SAV bit */
tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
-
- tcg_temp_free(temp);
- tcg_temp_free(t0);
}
static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
@@ -6617,13 +6610,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
@@ -6655,13 +6643,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
tcg_gen_movi_tl(cpu_PSW_AV, 0);
if (!tricore_feature(env, TRICORE_FEATURE_131)) {
/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
- tcg_gen_neg_tl(temp, temp3);
- /* use cpu_PSW_AV to compare against 0 */
- tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
- temp, temp3);
- tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
- tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
- temp2, cpu_gpr_d[r2]);
+ tcg_gen_abs_tl(temp, temp3);
+ tcg_gen_abs_tl(temp2, cpu_gpr_d[r2]);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
} else {
/* overflow = (D[b] == 0) */
--
2.17.1
next prev parent reply other threads:[~2019-05-04 5:53 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-04 5:52 [Qemu-devel] [PATCH v3 00/31] tcg vector improvements Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 01/31] tcg: Implement tcg_gen_gvec_3i() Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 04/31] tcg: Specify optional vector requirements with a list Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 05/31] tcg: Assert fixed_reg is read-only Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 07/31] tcg: Return bool success from tcg_out_mov Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 08/31] tcg: Support cross-class moves without instruction support Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 10/31] tcg: Manually expand INDEX_op_dup_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 11/31] tcg: Add tcg_out_dupm_vec to the backend interface Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 12/31] tcg/i386: Implement tcg_out_dupm_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 13/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 14/31] tcg: Add INDEX_op_dupm_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 15/31] tcg: Add gvec expanders for variable shift Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 16/31] tcg/i386: Support vector variable shift opcodes Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 17/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 18/31] tcg: Add gvec expanders for vector shift by scalar Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 21/31] tcg: Add support for vector " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 22/31] tcg/i386: Support " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 23/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 25/31] target/cris: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-08 19:54 ` David Hildenbrand
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 26/31] target/ppc: Use tcg_gen_abs_i32 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 28/31] target/s390x: Use tcg_gen_abs_i64 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` Richard Henderson [this message]
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 30/31] target/xtensa: Use tcg_gen_abs_i32 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:53 ` [Qemu-devel] [PATCH v3 31/31] tcg/aarch64: Do not advertise minmax for MO_64 Richard Henderson
2019-05-04 5:53 ` Richard Henderson
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