From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, david@redhat.com
Subject: [Qemu-devel] [PATCH v3 05/31] tcg: Assert fixed_reg is read-only
Date: Fri, 3 May 2019 22:52:34 -0700 [thread overview]
Message-ID: <20190504055300.18426-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190504055300.18426-1-richard.henderson@linaro.org>
The only fixed_reg is cpu_env, and it should not be modified
during any TB. Therefore code that tries to special-case moves
into a fixed_reg is dead. Remove it.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 87 +++++++++++++++++++++++++------------------------------
1 file changed, 40 insertions(+), 47 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f7bef51de8..70ca113c26 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3274,11 +3274,8 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
tcg_target_ulong val, TCGLifeData arg_life,
TCGRegSet preferred_regs)
{
- if (ots->fixed_reg) {
- /* For fixed registers, we do not do any constant propagation. */
- tcg_out_movi(s, ots->type, ots->reg, val);
- return;
- }
+ /* ENV should not be modified. */
+ tcg_debug_assert(!ots->fixed_reg);
/* The movi is not explicitly generated here. */
if (ots->val_type == TEMP_VAL_REG) {
@@ -3314,6 +3311,9 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
ots = arg_temp(op->args[0]);
ts = arg_temp(op->args[1]);
+ /* ENV should not be modified. */
+ tcg_debug_assert(!ots->fixed_reg);
+
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
itype = ts->type;
@@ -3338,7 +3338,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
}
tcg_debug_assert(ts->val_type == TEMP_VAL_REG);
- if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
+ if (IS_DEAD_ARG(0)) {
/* mov to a non-saved dead register makes no sense (even with
liveness analysis disabled). */
tcg_debug_assert(NEED_SYNC_ARG(0));
@@ -3351,7 +3351,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
}
temp_dead(s, ots);
} else {
- if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
+ if (IS_DEAD_ARG(1) && !ts->fixed_reg) {
/* the mov can be suppressed */
if (ots->val_type == TEMP_VAL_REG) {
s->reg_to_temp[ots->reg] = NULL;
@@ -3504,6 +3504,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = arg_temp(arg);
+
+ /* ENV should not be modified. */
+ tcg_debug_assert(!ts->fixed_reg);
+
if ((arg_ct->ct & TCG_CT_ALIAS)
&& !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
@@ -3512,29 +3516,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
} else {
- /* if fixed register, we try to use it */
- reg = ts->reg;
- if (ts->fixed_reg &&
- tcg_regset_test_reg(arg_ct->u.regs, reg)) {
- goto oarg_end;
- }
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
op->output_pref[k], ts->indirect_base);
}
tcg_regset_set_reg(o_allocated_regs, reg);
- /* if a fixed register is used, then a move will be done afterwards */
- if (!ts->fixed_reg) {
- if (ts->val_type == TEMP_VAL_REG) {
- s->reg_to_temp[ts->reg] = NULL;
- }
- ts->val_type = TEMP_VAL_REG;
- ts->reg = reg;
- /* temp value is modified, so the value kept in memory is
- potentially not the same */
- ts->mem_coherent = 0;
- s->reg_to_temp[reg] = ts;
+ if (ts->val_type == TEMP_VAL_REG) {
+ s->reg_to_temp[ts->reg] = NULL;
}
- oarg_end:
+ ts->val_type = TEMP_VAL_REG;
+ ts->reg = reg;
+ /*
+ * Temp value is modified, so the value kept in memory is
+ * potentially not the same.
+ */
+ ts->mem_coherent = 0;
+ s->reg_to_temp[reg] = ts;
new_args[i] = reg;
}
}
@@ -3550,10 +3546,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
- reg = new_args[i];
- if (ts->fixed_reg && ts->reg != reg) {
- tcg_out_mov(s, ts->type, ts->reg, reg);
- }
+
+ /* ENV should not be modified. */
+ tcg_debug_assert(!ts->fixed_reg);
+
if (NEED_SYNC_ARG(i)) {
temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i));
} else if (IS_DEAD_ARG(i)) {
@@ -3674,26 +3670,23 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
for(i = 0; i < nb_oargs; i++) {
arg = op->args[i];
ts = arg_temp(arg);
+
+ /* ENV should not be modified. */
+ tcg_debug_assert(!ts->fixed_reg);
+
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
-
- if (ts->fixed_reg) {
- if (ts->reg != reg) {
- tcg_out_mov(s, ts->type, ts->reg, reg);
- }
- } else {
- if (ts->val_type == TEMP_VAL_REG) {
- s->reg_to_temp[ts->reg] = NULL;
- }
- ts->val_type = TEMP_VAL_REG;
- ts->reg = reg;
- ts->mem_coherent = 0;
- s->reg_to_temp[reg] = ts;
- if (NEED_SYNC_ARG(i)) {
- temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i));
- } else if (IS_DEAD_ARG(i)) {
- temp_dead(s, ts);
- }
+ if (ts->val_type == TEMP_VAL_REG) {
+ s->reg_to_temp[ts->reg] = NULL;
+ }
+ ts->val_type = TEMP_VAL_REG;
+ ts->reg = reg;
+ ts->mem_coherent = 0;
+ s->reg_to_temp[reg] = ts;
+ if (NEED_SYNC_ARG(i)) {
+ temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i));
+ } else if (IS_DEAD_ARG(i)) {
+ temp_dead(s, ts);
}
}
}
--
2.17.1
next prev parent reply other threads:[~2019-05-04 5:53 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-04 5:52 [Qemu-devel] [PATCH v3 00/31] tcg vector improvements Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 01/31] tcg: Implement tcg_gen_gvec_3i() Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 04/31] tcg: Specify optional vector requirements with a list Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` Richard Henderson [this message]
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 05/31] tcg: Assert fixed_reg is read-only Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 07/31] tcg: Return bool success from tcg_out_mov Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 08/31] tcg: Support cross-class moves without instruction support Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 10/31] tcg: Manually expand INDEX_op_dup_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 11/31] tcg: Add tcg_out_dupm_vec to the backend interface Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 12/31] tcg/i386: Implement tcg_out_dupm_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 13/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 14/31] tcg: Add INDEX_op_dupm_vec Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 15/31] tcg: Add gvec expanders for variable shift Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 16/31] tcg/i386: Support vector variable shift opcodes Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 17/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 18/31] tcg: Add gvec expanders for vector shift by scalar Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 21/31] tcg: Add support for vector " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 22/31] tcg/i386: Support " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 23/31] tcg/aarch64: " Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 25/31] target/cris: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-08 19:54 ` David Hildenbrand
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 26/31] target/ppc: Use tcg_gen_abs_i32 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 28/31] target/s390x: Use tcg_gen_abs_i64 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:52 ` [Qemu-devel] [PATCH v3 30/31] target/xtensa: Use tcg_gen_abs_i32 Richard Henderson
2019-05-04 5:52 ` Richard Henderson
2019-05-04 5:53 ` [Qemu-devel] [PATCH v3 31/31] tcg/aarch64: Do not advertise minmax for MO_64 Richard Henderson
2019-05-04 5:53 ` Richard Henderson
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