From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E785C004C9 for ; Tue, 7 May 2019 16:44:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03C62205C9 for ; Tue, 7 May 2019 16:44:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03C62205C9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([127.0.0.1]:49910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hO3Ch-0001hN-7Z for qemu-devel@archiver.kernel.org; Tue, 07 May 2019 12:44:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hO35x-0003Q2-N4 for qemu-devel@nongnu.org; Tue, 07 May 2019 12:37:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hO35w-0004MA-NV for qemu-devel@nongnu.org; Tue, 07 May 2019 12:37:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52434) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hO35u-0004Ib-6f; Tue, 07 May 2019 12:37:30 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 47FDF30917F0; Tue, 7 May 2019 16:37:29 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-58.brq.redhat.com [10.40.204.58]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 519028162; Tue, 7 May 2019 16:37:15 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Markus Armbruster , Thomas Huth , qemu-devel@nongnu.org, Eduardo Habkost Date: Tue, 7 May 2019 18:34:11 +0200 Message-Id: <20190507163416.24647-12-philmd@redhat.com> In-Reply-To: <20190507163416.24647-1-philmd@redhat.com> References: <20190507163416.24647-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Tue, 07 May 2019 16:37:29 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 11/16] hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , Antony Pavlov , Paul Burton , Andrew Jeffery , Alistair Francis , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Joel Stanley , Aleksandar Rikalo , qemu-arm@nongnu.org, Peter Chubb , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Aleksandar Markovic , "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Inter Processor Interrupt is a block part of the SoC, not the "machine" (talking about machine is borderline with the PMU, since it is embedded into the ZynqMP SoC, but currentl QEMU doesn't support multi-arch cores). Move the IPI state to the SoC state, this will simplify the review of the next patch. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/microblaze/xlnx-zynqmp-pmu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-= pmu.c index 57dc1ccd429..eba9945c19b 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -55,6 +55,7 @@ typedef struct XlnxZynqMPPMUSoCState { /*< public >*/ MicroBlazeCPU cpu; XlnxPMUIOIntc intc; + XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS]; } XlnxZynqMPPMUSoCState; =20 =20 @@ -144,7 +145,6 @@ static void xlnx_zynqmp_pmu_init(MachineState *machin= e) MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *pmu_rom =3D g_new(MemoryRegion, 1); MemoryRegion *pmu_ram =3D g_new(MemoryRegion, 1); - XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS]; qemu_irq irq[32]; int i; =20 @@ -172,16 +172,16 @@ static void xlnx_zynqmp_pmu_init(MachineState *mach= ine) =20 /* Create and connect the IPI device */ for (i =3D 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { - ipi[i] =3D g_new0(XlnxZynqMPIPI, 1); - object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQM= P_IPI); - qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default()); + object_initialize(&pmu->ipi[i], sizeof(XlnxZynqMPIPI), + TYPE_XLNX_ZYNQMP_IPI); + qdev_set_parent_bus(DEVICE(&pmu->ipi[i]), sysbus_get_default()); } =20 for (i =3D 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { - object_property_set_bool(OBJECT(ipi[i]), true, "realized", + object_property_set_bool(OBJECT(&pmu->ipi[i]), true, "realized", &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]); - sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]); + sysbus_mmio_map(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, ipi_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&pmu->ipi[i]), 0, irq[ipi_irq[= i]]); } =20 /* Load the kernel */ --=20 2.20.1