* [Qemu-devel] [PATCH v3 1/5] pcie: Remove redundant test in pcie_mmcfg_data_{read, write}()
2019-05-07 6:23 [Qemu-devel] [PATCH v3 0/5] Simplify some not-really-necessary PCI bus callbacks David Gibson
@ 2019-05-07 6:23 ` David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 2/5] pci: Simplify pci_bus_is_root() David Gibson
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2019-05-07 6:23 UTC (permalink / raw)
To: qemu-devel, mst; +Cc: aik, Mark Cave-Ayland, Greg Kurz, qemu-ppc, David Gibson
These functions have an explicit test for accesses above the device's
config size. But pci_host_config_{read,write}_common() which they're
about to call already have checks against the config space limit and
do the right thing. So, remove the redundant tests.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/pci/pcie_host.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index 553db56778..1ee4945a6d 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -47,11 +47,6 @@ static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
}
addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
limit = pci_config_size(pci_dev);
- if (limit <= addr) {
- /* conventional pci device can be behind pcie-to-pci bridge.
- 256 <= addr < 4K has no effects. */
- return;
- }
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
@@ -70,11 +65,6 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
}
addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
limit = pci_config_size(pci_dev);
- if (limit <= addr) {
- /* conventional pci device can be behind pcie-to-pci bridge.
- 256 <= addr < 4K has no effects. */
- return ~0x0;
- }
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
--
2.21.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH v3 2/5] pci: Simplify pci_bus_is_root()
2019-05-07 6:23 [Qemu-devel] [PATCH v3 0/5] Simplify some not-really-necessary PCI bus callbacks David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 1/5] pcie: Remove redundant test in pcie_mmcfg_data_{read, write}() David Gibson
@ 2019-05-07 6:23 ` David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 3/5] pcie: Simplify pci_adjust_config_limit() David Gibson
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2019-05-07 6:23 UTC (permalink / raw)
To: qemu-devel, mst
Cc: aik, Mark Cave-Ayland, Greg Kurz, Peter Xu, qemu-ppc,
Marcel Apfelbaum, David Gibson
pci_bus_is_root() currently relies on a method in the PCIBusClass.
But it's always known if a PCI bus is a root bus when we create it, so
using a dynamic method is overkill.
This replaces it with an IS_ROOT bit in a new flags field, which is set on
root buses and otherwise clear. As a bonus this removes the special
is_root logic from pci_expander_bridge, since it already creates its bus
as a root bus.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/pci-bridge/pci_expander_bridge.c | 6 ------
hw/pci/pci.c | 14 ++------------
hw/virtio/virtio-pci.c | 1 +
include/hw/pci/pci.h | 1 -
include/hw/pci/pci_bus.h | 12 +++++++++++-
5 files changed, 14 insertions(+), 20 deletions(-)
diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c
index e62de4218f..ca66bc721a 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -66,11 +66,6 @@ static int pxb_bus_num(PCIBus *bus)
return pxb->bus_nr;
}
-static bool pxb_is_root(PCIBus *bus)
-{
- return true; /* by definition */
-}
-
static uint16_t pxb_bus_numa_node(PCIBus *bus)
{
PXBDev *pxb = convert_to_pxb(bus->parent_dev);
@@ -83,7 +78,6 @@ static void pxb_bus_class_init(ObjectClass *class, void *data)
PCIBusClass *pbc = PCI_BUS_CLASS(class);
pbc->bus_num = pxb_bus_num;
- pbc->is_root = pxb_is_root;
pbc->numa_node = pxb_bus_numa_node;
}
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index a78023f669..b386777045 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -129,14 +129,9 @@ static void pci_bus_unrealize(BusState *qbus, Error **errp)
vmstate_unregister(NULL, &vmstate_pcibus, bus);
}
-static bool pcibus_is_root(PCIBus *bus)
-{
- return !bus->parent_dev;
-}
-
static int pcibus_num(PCIBus *bus)
{
- if (pcibus_is_root(bus)) {
+ if (pci_bus_is_root(bus)) {
return 0; /* pci host bridge */
}
return bus->parent_dev->config[PCI_SECONDARY_BUS];
@@ -164,7 +159,6 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
k->unrealize = pci_bus_unrealize;
k->reset = pcibus_reset;
- pbc->is_root = pcibus_is_root;
pbc->bus_num = pcibus_num;
pbc->numa_node = pcibus_numa_node;
pbc->allows_extended_config_space = pcibus_allows_extended_config_space;
@@ -398,6 +392,7 @@ static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
bus->slot_reserved_mask = 0x0;
bus->address_space_mem = address_space_mem;
bus->address_space_io = address_space_io;
+ bus->flags |= PCI_BUS_IS_ROOT;
/* host bridge */
QLIST_INIT(&bus->child);
@@ -415,11 +410,6 @@ bool pci_bus_is_express(PCIBus *bus)
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
}
-bool pci_bus_is_root(PCIBus *bus)
-{
- return PCI_BUS_GET_CLASS(bus)->is_root(bus);
-}
-
bool pci_bus_allows_extended_config_space(PCIBus *bus)
{
return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus);
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index cb44e19b67..942173d830 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -20,6 +20,7 @@
#include "standard-headers/linux/virtio_pci.h"
#include "hw/virtio/virtio.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_bus.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/pci/msi.h"
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index fdd4c43d3a..edf44de21d 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -395,7 +395,6 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define TYPE_PCIE_BUS "PCIE"
bool pci_bus_is_express(PCIBus *bus);
-bool pci_bus_is_root(PCIBus *bus);
bool pci_bus_allows_extended_config_space(PCIBus *bus);
void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index f6df834170..aea98d5040 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -15,14 +15,19 @@ typedef struct PCIBusClass {
BusClass parent_class;
/*< public >*/
- bool (*is_root)(PCIBus *bus);
int (*bus_num)(PCIBus *bus);
uint16_t (*numa_node)(PCIBus *bus);
bool (*allows_extended_config_space)(PCIBus *bus);
} PCIBusClass;
+enum PCIBusFlags {
+ /* This bus is the root of a PCI domain */
+ PCI_BUS_IS_ROOT = 0x0001,
+};
+
struct PCIBus {
BusState qbus;
+ enum PCIBusFlags flags;
PCIIOMMUFunc iommu_fn;
void *iommu_opaque;
uint8_t devfn_min;
@@ -47,4 +52,9 @@ struct PCIBus {
Notifier machine_done;
};
+static inline bool pci_bus_is_root(PCIBus *bus)
+{
+ return !!(bus->flags & PCI_BUS_IS_ROOT);
+}
+
#endif /* QEMU_PCI_BUS_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH v3 3/5] pcie: Simplify pci_adjust_config_limit()
2019-05-07 6:23 [Qemu-devel] [PATCH v3 0/5] Simplify some not-really-necessary PCI bus callbacks David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 1/5] pcie: Remove redundant test in pcie_mmcfg_data_{read, write}() David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 2/5] pci: Simplify pci_bus_is_root() David Gibson
@ 2019-05-07 6:23 ` David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 4/5] pci: Make is_bridge a bool David Gibson
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller David Gibson
4 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2019-05-07 6:23 UTC (permalink / raw)
To: qemu-devel, mst; +Cc: aik, Mark Cave-Ayland, Greg Kurz, qemu-ppc, David Gibson
Since c2077e2c "pci: Adjust PCI config limit based on bus topology",
pci_adjust_config_limit() has been used in the config space read and write
paths to only permit access to extended config space on buses which permit
it. Specifically it prevents access on devices below a vanilla-PCI bus via
some combination of bridges, even if both the host bridge and the device
itself are PCI-E.
It accomplishes this with a somewhat complex call up the chain of bridges
to see if any of them prohibit extended config space access. This is
overly complex, since we can always know if the bus will support such
access at the point it is constructed.
This patch simplifies the test by using a flag in the PCIBus instance
indicating whether extended configuration space is accessible. It is
false for vanilla PCI buses. For PCI-E buses, it is true for root
buses and equal to the parent bus's's capability otherwise.
For the special case of sPAPR's paravirtualized PCI root bus, which
acts mostly like vanilla PCI, but does allow extended config space
access, we override the default value of the flag from the host bridge
code.
This should cause no behavioural change.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/pci/pci.c | 41 ++++++++++++++++++++++------------------
hw/pci/pci_host.c | 13 +++----------
hw/ppc/spapr_pci.c | 34 ++++++++++-----------------------
include/hw/pci/pci.h | 1 -
include/hw/pci/pci_bus.h | 8 +++++++-
5 files changed, 43 insertions(+), 54 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index b386777045..7e5f8d001b 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -120,6 +120,27 @@ static void pci_bus_realize(BusState *qbus, Error **errp)
vmstate_register(NULL, -1, &vmstate_pcibus, bus);
}
+static void pcie_bus_realize(BusState *qbus, Error **errp)
+{
+ PCIBus *bus = PCI_BUS(qbus);
+
+ pci_bus_realize(qbus, errp);
+
+ /*
+ * A PCI-E bus can support extended config space if it's the root
+ * bus, or if the bus/bridge above it does as well
+ */
+ if (pci_bus_is_root(bus)) {
+ bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ } else {
+ PCIBus *parent_bus = pci_get_bus(bus->parent_dev);
+
+ if (pci_bus_allows_extended_config_space(parent_bus)) {
+ bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ }
+ }
+}
+
static void pci_bus_unrealize(BusState *qbus, Error **errp)
{
PCIBus *bus = PCI_BUS(qbus);
@@ -142,11 +163,6 @@ static uint16_t pcibus_numa_node(PCIBus *bus)
return NUMA_NODE_UNASSIGNED;
}
-static bool pcibus_allows_extended_config_space(PCIBus *bus)
-{
- return false;
-}
-
static void pci_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
@@ -161,7 +177,6 @@ static void pci_bus_class_init(ObjectClass *klass, void *data)
pbc->bus_num = pcibus_num;
pbc->numa_node = pcibus_numa_node;
- pbc->allows_extended_config_space = pcibus_allows_extended_config_space;
}
static const TypeInfo pci_bus_info = {
@@ -182,16 +197,11 @@ static const TypeInfo conventional_pci_interface_info = {
.parent = TYPE_INTERFACE,
};
-static bool pciebus_allows_extended_config_space(PCIBus *bus)
-{
- return true;
-}
-
static void pcie_bus_class_init(ObjectClass *klass, void *data)
{
- PCIBusClass *pbc = PCI_BUS_CLASS(klass);
+ BusClass *k = BUS_CLASS(klass);
- pbc->allows_extended_config_space = pciebus_allows_extended_config_space;
+ k->realize = pcie_bus_realize;
}
static const TypeInfo pcie_bus_info = {
@@ -410,11 +420,6 @@ bool pci_bus_is_express(PCIBus *bus)
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
}
-bool pci_bus_allows_extended_config_space(PCIBus *bus)
-{
- return PCI_BUS_GET_CLASS(bus)->allows_extended_config_space(bus);
-}
-
void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
const char *name,
MemoryRegion *address_space_mem,
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index 9d64b2e12f..5f3497256c 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -53,16 +53,9 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
{
- if (*limit > PCI_CONFIG_SPACE_SIZE) {
- if (!pci_bus_allows_extended_config_space(bus)) {
- *limit = PCI_CONFIG_SPACE_SIZE;
- return;
- }
-
- if (!pci_bus_is_root(bus)) {
- PCIDevice *bridge = pci_bridge_get_device(bus);
- pci_adjust_config_limit(pci_get_bus(bridge), limit);
- }
+ if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
+ !pci_bus_allows_extended_config_space(bus)) {
+ *limit = PCI_CONFIG_SPACE_SIZE;
}
}
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 97961b0128..9cf2c41b8c 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -1626,28 +1626,6 @@ static void spapr_phb_unrealize(DeviceState *dev, Error **errp)
memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
}
-static bool spapr_phb_allows_extended_config_space(PCIBus *bus)
-{
- SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(BUS(bus)->parent);
-
- return sphb->pcie_ecs;
-}
-
-static void spapr_phb_root_bus_class_init(ObjectClass *klass, void *data)
-{
- PCIBusClass *pbc = PCI_BUS_CLASS(klass);
-
- pbc->allows_extended_config_space = spapr_phb_allows_extended_config_space;
-}
-
-#define TYPE_SPAPR_PHB_ROOT_BUS "pci"
-
-static const TypeInfo spapr_phb_root_bus_info = {
- .name = TYPE_SPAPR_PHB_ROOT_BUS,
- .parent = TYPE_PCI_BUS,
- .class_init = spapr_phb_root_bus_class_init,
-};
-
static void spapr_phb_realize(DeviceState *dev, Error **errp)
{
/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
@@ -1753,7 +1731,16 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
&sphb->memspace, &sphb->iospace,
PCI_DEVFN(0, 0), PCI_NUM_PINS,
- TYPE_SPAPR_PHB_ROOT_BUS);
+ TYPE_PCI_BUS);
+
+ /*
+ * Despite resembling a vanilla PCI bus in most ways, the PAPR
+ * para-virtualized PCI bus *does* permit PCI-E extended config
+ * space access
+ */
+ if (sphb->pcie_ecs) {
+ bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ }
phb->bus = bus;
qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL);
@@ -2348,7 +2335,6 @@ void spapr_pci_rtas_init(void)
static void spapr_pci_register_types(void)
{
type_register_static(&spapr_phb_info);
- type_register_static(&spapr_phb_root_bus_info);
}
type_init(spapr_pci_register_types)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index edf44de21d..da20c915ef 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -395,7 +395,6 @@ typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
#define TYPE_PCIE_BUS "PCIE"
bool pci_bus_is_express(PCIBus *bus);
-bool pci_bus_allows_extended_config_space(PCIBus *bus);
void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
const char *name,
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index aea98d5040..0714f578af 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -17,12 +17,13 @@ typedef struct PCIBusClass {
int (*bus_num)(PCIBus *bus);
uint16_t (*numa_node)(PCIBus *bus);
- bool (*allows_extended_config_space)(PCIBus *bus);
} PCIBusClass;
enum PCIBusFlags {
/* This bus is the root of a PCI domain */
PCI_BUS_IS_ROOT = 0x0001,
+ /* PCIe extended configuration space is accessible on this bus */
+ PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
};
struct PCIBus {
@@ -57,4 +58,9 @@ static inline bool pci_bus_is_root(PCIBus *bus)
return !!(bus->flags & PCI_BUS_IS_ROOT);
}
+static inline bool pci_bus_allows_extended_config_space(PCIBus *bus)
+{
+ return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE);
+}
+
#endif /* QEMU_PCI_BUS_H */
--
2.21.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH v3 4/5] pci: Make is_bridge a bool
2019-05-07 6:23 [Qemu-devel] [PATCH v3 0/5] Simplify some not-really-necessary PCI bus callbacks David Gibson
` (2 preceding siblings ...)
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 3/5] pcie: Simplify pci_adjust_config_limit() David Gibson
@ 2019-05-07 6:23 ` David Gibson
2019-05-07 10:02 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller David Gibson
4 siblings, 1 reply; 9+ messages in thread
From: David Gibson @ 2019-05-07 6:23 UTC (permalink / raw)
To: qemu-devel, mst; +Cc: aik, qemu-ppc, Mark Cave-Ayland, David Gibson
The is_bridge field in PCIDevice acts as a bool, but is declared as an int.
Declare it as a bool for clarity, and change everything that writes it to
use true/false instead of 0/1 to match.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-bridge/dec.c | 4 ++--
hw/pci-bridge/i82801b11.c | 2 +-
hw/pci-bridge/pci_bridge_dev.c | 2 +-
hw/pci-bridge/pcie_pci_bridge.c | 2 +-
hw/pci-bridge/pcie_root_port.c | 2 +-
hw/pci-bridge/simba.c | 2 +-
hw/pci-bridge/xio3130_downstream.c | 2 +-
hw/pci-bridge/xio3130_upstream.c | 2 +-
include/hw/pci/pci.h | 2 +-
9 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c
index 8484bfd434..ca40253730 100644
--- a/hw/pci-bridge/dec.c
+++ b/hw/pci-bridge/dec.c
@@ -68,7 +68,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_DEC;
k->device_id = PCI_DEVICE_ID_DEC_21154;
k->config_write = pci_bridge_write_config;
- k->is_bridge = 1;
+ k->is_bridge = true;
dc->desc = "DEC 21154 PCI-PCI bridge";
dc->reset = pci_bridge_reset;
dc->vmsd = &vmstate_pci_device;
@@ -129,7 +129,7 @@ static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_DEC_21154;
k->revision = 0x02;
k->class_id = PCI_CLASS_BRIDGE_PCI;
- k->is_bridge = 1;
+ k->is_bridge = true;
/*
* PCI-facing part of the host bridge, not usable without the
* host-facing part, which can't be device_add'ed, yet.
diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
index 10e590e5c6..6d8b0f54a7 100644
--- a/hw/pci-bridge/i82801b11.c
+++ b/hw/pci-bridge/i82801b11.c
@@ -90,7 +90,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->is_bridge = 1;
+ k->is_bridge = true;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
k->revision = ICH9_D2P_A2_REVISION;
diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
index ff6b8323da..c56ed1f52f 100644
--- a/hw/pci-bridge/pci_bridge_dev.c
+++ b/hw/pci-bridge/pci_bridge_dev.c
@@ -253,7 +253,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
k->class_id = PCI_CLASS_BRIDGE_PCI;
- k->is_bridge = 1,
+ k->is_bridge = true;
dc->desc = "Standard PCI Bridge";
dc->reset = qdev_pci_bridge_dev_reset;
dc->props = pci_bridge_dev_properties;
diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c
index d491b40d04..9a4fba413a 100644
--- a/hw/pci-bridge/pcie_pci_bridge.c
+++ b/hw/pci-bridge/pcie_pci_bridge.c
@@ -143,7 +143,7 @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
- k->is_bridge = 1;
+ k->is_bridge = true;
k->vendor_id = PCI_VENDOR_ID_REDHAT;
k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
k->realize = pcie_pci_bridge_realize;
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index e94d918b6d..be3f4d5e03 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -162,7 +162,7 @@ static void rp_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->is_bridge = 1;
+ k->is_bridge = true;
k->config_write = rp_write_config;
k->realize = rp_realize;
k->exit = rp_exit;
diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
index dea4c8c5e7..7cf0d6e047 100644
--- a/hw/pci-bridge/simba.c
+++ b/hw/pci-bridge/simba.c
@@ -76,7 +76,7 @@ static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
k->revision = 0x11;
k->config_write = pci_bridge_write_config;
- k->is_bridge = 1;
+ k->is_bridge = true;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->reset = pci_bridge_reset;
dc->vmsd = &vmstate_pci_device;
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 467bbabe4c..ab2a51e15d 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -152,7 +152,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->is_bridge = 1;
+ k->is_bridge = true;
k->config_write = xio3130_downstream_write_config;
k->realize = xio3130_downstream_realize;
k->exit = xio3130_downstream_exitfn;
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index b524908cf1..1d41a49ab0 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -126,7 +126,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->is_bridge = 1;
+ k->is_bridge = true;
k->config_write = xio3130_upstream_write_config;
k->realize = xio3130_upstream_realize;
k->exit = xio3130_upstream_exitfn;
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index da20c915ef..d082707dfa 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -234,7 +234,7 @@ typedef struct PCIDeviceClass {
* This doesn't mean pci host switch.
* When card bus bridge is supported, this would be enhanced.
*/
- int is_bridge;
+ bool is_bridge;
/* rom bar */
const char *romfile;
--
2.21.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 4/5] pci: Make is_bridge a bool
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 4/5] pci: Make is_bridge a bool David Gibson
@ 2019-05-07 10:02 ` Greg Kurz
0 siblings, 0 replies; 9+ messages in thread
From: Greg Kurz @ 2019-05-07 10:02 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, mst
On Tue, 7 May 2019 16:23:15 +1000
David Gibson <david@gibson.dropbear.id.au> wrote:
> The is_bridge field in PCIDevice acts as a bool, but is declared as an int.
> Declare it as a bool for clarity, and change everything that writes it to
> use true/false instead of 0/1 to match.
>
Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/pci-bridge/dec.c | 4 ++--
> hw/pci-bridge/i82801b11.c | 2 +-
> hw/pci-bridge/pci_bridge_dev.c | 2 +-
> hw/pci-bridge/pcie_pci_bridge.c | 2 +-
> hw/pci-bridge/pcie_root_port.c | 2 +-
> hw/pci-bridge/simba.c | 2 +-
> hw/pci-bridge/xio3130_downstream.c | 2 +-
> hw/pci-bridge/xio3130_upstream.c | 2 +-
> include/hw/pci/pci.h | 2 +-
> 9 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c
> index 8484bfd434..ca40253730 100644
> --- a/hw/pci-bridge/dec.c
> +++ b/hw/pci-bridge/dec.c
> @@ -68,7 +68,7 @@ static void dec_21154_pci_bridge_class_init(ObjectClass *klass, void *data)
> k->vendor_id = PCI_VENDOR_ID_DEC;
> k->device_id = PCI_DEVICE_ID_DEC_21154;
> k->config_write = pci_bridge_write_config;
> - k->is_bridge = 1;
> + k->is_bridge = true;
> dc->desc = "DEC 21154 PCI-PCI bridge";
> dc->reset = pci_bridge_reset;
> dc->vmsd = &vmstate_pci_device;
> @@ -129,7 +129,7 @@ static void dec_21154_pci_host_class_init(ObjectClass *klass, void *data)
> k->device_id = PCI_DEVICE_ID_DEC_21154;
> k->revision = 0x02;
> k->class_id = PCI_CLASS_BRIDGE_PCI;
> - k->is_bridge = 1;
> + k->is_bridge = true;
> /*
> * PCI-facing part of the host bridge, not usable without the
> * host-facing part, which can't be device_add'ed, yet.
> diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c
> index 10e590e5c6..6d8b0f54a7 100644
> --- a/hw/pci-bridge/i82801b11.c
> +++ b/hw/pci-bridge/i82801b11.c
> @@ -90,7 +90,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> - k->is_bridge = 1;
> + k->is_bridge = true;
> k->vendor_id = PCI_VENDOR_ID_INTEL;
> k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
> k->revision = ICH9_D2P_A2_REVISION;
> diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
> index ff6b8323da..c56ed1f52f 100644
> --- a/hw/pci-bridge/pci_bridge_dev.c
> +++ b/hw/pci-bridge/pci_bridge_dev.c
> @@ -253,7 +253,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
> k->vendor_id = PCI_VENDOR_ID_REDHAT;
> k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
> k->class_id = PCI_CLASS_BRIDGE_PCI;
> - k->is_bridge = 1,
> + k->is_bridge = true;
> dc->desc = "Standard PCI Bridge";
> dc->reset = qdev_pci_bridge_dev_reset;
> dc->props = pci_bridge_dev_properties;
> diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c
> index d491b40d04..9a4fba413a 100644
> --- a/hw/pci-bridge/pcie_pci_bridge.c
> +++ b/hw/pci-bridge/pcie_pci_bridge.c
> @@ -143,7 +143,7 @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
> HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
>
> - k->is_bridge = 1;
> + k->is_bridge = true;
> k->vendor_id = PCI_VENDOR_ID_REDHAT;
> k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
> k->realize = pcie_pci_bridge_realize;
> diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
> index e94d918b6d..be3f4d5e03 100644
> --- a/hw/pci-bridge/pcie_root_port.c
> +++ b/hw/pci-bridge/pcie_root_port.c
> @@ -162,7 +162,7 @@ static void rp_class_init(ObjectClass *klass, void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
>
> - k->is_bridge = 1;
> + k->is_bridge = true;
> k->config_write = rp_write_config;
> k->realize = rp_realize;
> k->exit = rp_exit;
> diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c
> index dea4c8c5e7..7cf0d6e047 100644
> --- a/hw/pci-bridge/simba.c
> +++ b/hw/pci-bridge/simba.c
> @@ -76,7 +76,7 @@ static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
> k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
> k->revision = 0x11;
> k->config_write = pci_bridge_write_config;
> - k->is_bridge = 1;
> + k->is_bridge = true;
> set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
> dc->reset = pci_bridge_reset;
> dc->vmsd = &vmstate_pci_device;
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 467bbabe4c..ab2a51e15d 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -152,7 +152,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
>
> - k->is_bridge = 1;
> + k->is_bridge = true;
> k->config_write = xio3130_downstream_write_config;
> k->realize = xio3130_downstream_realize;
> k->exit = xio3130_downstream_exitfn;
> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
> index b524908cf1..1d41a49ab0 100644
> --- a/hw/pci-bridge/xio3130_upstream.c
> +++ b/hw/pci-bridge/xio3130_upstream.c
> @@ -126,7 +126,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
> DeviceClass *dc = DEVICE_CLASS(klass);
> PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
>
> - k->is_bridge = 1;
> + k->is_bridge = true;
> k->config_write = xio3130_upstream_write_config;
> k->realize = xio3130_upstream_realize;
> k->exit = xio3130_upstream_exitfn;
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index da20c915ef..d082707dfa 100644
> --- a/include/hw/pci/pci.h
> +++ b/include/hw/pci/pci.h
> @@ -234,7 +234,7 @@ typedef struct PCIDeviceClass {
> * This doesn't mean pci host switch.
> * When card bus bridge is supported, this would be enhanced.
> */
> - int is_bridge;
> + bool is_bridge;
>
> /* rom bar */
> const char *romfile;
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller
2019-05-07 6:23 [Qemu-devel] [PATCH v3 0/5] Simplify some not-really-necessary PCI bus callbacks David Gibson
` (3 preceding siblings ...)
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 4/5] pci: Make is_bridge a bool David Gibson
@ 2019-05-07 6:23 ` David Gibson
2019-05-07 10:21 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
4 siblings, 1 reply; 9+ messages in thread
From: David Gibson @ 2019-05-07 6:23 UTC (permalink / raw)
To: qemu-devel, mst; +Cc: aik, qemu-ppc, Mark Cave-Ayland, David Gibson
The only remaining caller of pci_get_bus_devfn() is pci_nic_init_nofail(),
itself an old compatibility function. Fold the two together to avoid
re-using the stale interface.
While we're there replace the explicit fprintf()s with error_report().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci/pci.c | 61 +++++++++++++++++++++++++---------------------------
1 file changed, 29 insertions(+), 32 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 7e5f8d001b..90e2743185 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -723,37 +723,6 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
return 0;
}
-static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
- const char *devaddr)
-{
- int dom, bus;
- unsigned slot;
-
- if (!root) {
- fprintf(stderr, "No primary PCI bus\n");
- return NULL;
- }
-
- assert(!root->parent_dev);
-
- if (!devaddr) {
- *devfnp = -1;
- return pci_find_bus_nr(root, 0);
- }
-
- if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
- return NULL;
- }
-
- if (dom != 0) {
- fprintf(stderr, "No support for non-zero PCI domains\n");
- return NULL;
- }
-
- *devfnp = PCI_DEVFN(slot, 0);
- return pci_find_bus_nr(root, bus);
-}
-
static void pci_init_cmask(PCIDevice *dev)
{
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
@@ -1895,6 +1864,8 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
DeviceState *dev;
int devfn;
int i;
+ int dom, busnr;
+ unsigned slot;
if (nd->model && !strcmp(nd->model, "virtio")) {
g_free(nd->model);
@@ -1928,7 +1899,33 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
exit(1);
}
- bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
+ if (!rootbus) {
+ error_report("No primary PCI bus");
+ exit(1);
+ }
+
+ assert(!rootbus->parent_dev);
+
+ if (!devaddr) {
+ devfn = -1;
+ busnr = 0;
+ bus = pci_find_bus_nr(rootbus, 0);
+ } else {
+ if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
+ error_report("Invalid PCI device address %s for device %s",
+ devaddr, nd->model);
+ exit(1);
+ }
+
+ if (dom != 0) {
+ error_report("No support for non-zero PCI domains");
+ exit(1);
+ }
+
+ devfn = PCI_DEVFN(slot, 0);
+ }
+
+ bus = pci_find_bus_nr(rootbus, busnr);
if (!bus) {
error_report("Invalid PCI device address %s for device %s",
devaddr, nd->model);
--
2.21.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller
2019-05-07 6:23 ` [Qemu-devel] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller David Gibson
@ 2019-05-07 10:21 ` Greg Kurz
2019-05-08 2:11 ` David Gibson
0 siblings, 1 reply; 9+ messages in thread
From: Greg Kurz @ 2019-05-07 10:21 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, mst
On Tue, 7 May 2019 16:23:16 +1000
David Gibson <david@gibson.dropbear.id.au> wrote:
> The only remaining caller of pci_get_bus_devfn() is pci_nic_init_nofail(),
> itself an old compatibility function. Fold the two together to avoid
> re-using the stale interface.
>
> While we're there replace the explicit fprintf()s with error_report().
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/pci/pci.c | 61 +++++++++++++++++++++++++---------------------------
> 1 file changed, 29 insertions(+), 32 deletions(-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index 7e5f8d001b..90e2743185 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -723,37 +723,6 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
> return 0;
> }
>
> -static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
> - const char *devaddr)
> -{
> - int dom, bus;
> - unsigned slot;
> -
> - if (!root) {
> - fprintf(stderr, "No primary PCI bus\n");
> - return NULL;
> - }
> -
> - assert(!root->parent_dev);
> -
> - if (!devaddr) {
> - *devfnp = -1;
> - return pci_find_bus_nr(root, 0);
> - }
> -
> - if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
> - return NULL;
> - }
> -
> - if (dom != 0) {
> - fprintf(stderr, "No support for non-zero PCI domains\n");
> - return NULL;
> - }
> -
> - *devfnp = PCI_DEVFN(slot, 0);
> - return pci_find_bus_nr(root, bus);
> -}
> -
> static void pci_init_cmask(PCIDevice *dev)
> {
> pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
> @@ -1895,6 +1864,8 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
> DeviceState *dev;
> int devfn;
> int i;
> + int dom, busnr;
> + unsigned slot;
>
> if (nd->model && !strcmp(nd->model, "virtio")) {
> g_free(nd->model);
> @@ -1928,7 +1899,33 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
> exit(1);
> }
>
> - bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
> + if (!rootbus) {
> + error_report("No primary PCI bus");
> + exit(1);
> + }
> +
> + assert(!rootbus->parent_dev);
> +
> + if (!devaddr) {
> + devfn = -1;
> + busnr = 0;
> + bus = pci_find_bus_nr(rootbus, 0);
This line isn't needed since it is done below...
> + } else {
> + if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
> + error_report("Invalid PCI device address %s for device %s",
> + devaddr, nd->model);
> + exit(1);
> + }
> +
> + if (dom != 0) {
> + error_report("No support for non-zero PCI domains");
> + exit(1);
> + }
> +
> + devfn = PCI_DEVFN(slot, 0);
> + }
> +
> + bus = pci_find_bus_nr(rootbus, busnr);
... here.
> if (!bus) {
> error_report("Invalid PCI device address %s for device %s",
> devaddr, nd->model);
Maybe output a different message from the one for pci_parse_devaddr()
failures ? Here, the address is supposed to be well formatted but we
couldn't find the requested bus.
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 5/5] pci: Fold pci_get_bus_devfn() into its sole caller
2019-05-07 10:21 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
@ 2019-05-08 2:11 ` David Gibson
0 siblings, 0 replies; 9+ messages in thread
From: David Gibson @ 2019-05-08 2:11 UTC (permalink / raw)
To: Greg Kurz; +Cc: qemu-ppc, qemu-devel, mst
[-- Attachment #1: Type: text/plain, Size: 4058 bytes --]
On Tue, May 07, 2019 at 12:21:29PM +0200, Greg Kurz wrote:
> On Tue, 7 May 2019 16:23:16 +1000
> David Gibson <david@gibson.dropbear.id.au> wrote:
>
> > The only remaining caller of pci_get_bus_devfn() is pci_nic_init_nofail(),
> > itself an old compatibility function. Fold the two together to avoid
> > re-using the stale interface.
> >
> > While we're there replace the explicit fprintf()s with error_report().
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > hw/pci/pci.c | 61 +++++++++++++++++++++++++---------------------------
> > 1 file changed, 29 insertions(+), 32 deletions(-)
> >
> > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > index 7e5f8d001b..90e2743185 100644
> > --- a/hw/pci/pci.c
> > +++ b/hw/pci/pci.c
> > @@ -723,37 +723,6 @@ static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
> > return 0;
> > }
> >
> > -static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
> > - const char *devaddr)
> > -{
> > - int dom, bus;
> > - unsigned slot;
> > -
> > - if (!root) {
> > - fprintf(stderr, "No primary PCI bus\n");
> > - return NULL;
> > - }
> > -
> > - assert(!root->parent_dev);
> > -
> > - if (!devaddr) {
> > - *devfnp = -1;
> > - return pci_find_bus_nr(root, 0);
> > - }
> > -
> > - if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
> > - return NULL;
> > - }
> > -
> > - if (dom != 0) {
> > - fprintf(stderr, "No support for non-zero PCI domains\n");
> > - return NULL;
> > - }
> > -
> > - *devfnp = PCI_DEVFN(slot, 0);
> > - return pci_find_bus_nr(root, bus);
> > -}
> > -
> > static void pci_init_cmask(PCIDevice *dev)
> > {
> > pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
> > @@ -1895,6 +1864,8 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
> > DeviceState *dev;
> > int devfn;
> > int i;
> > + int dom, busnr;
> > + unsigned slot;
> >
> > if (nd->model && !strcmp(nd->model, "virtio")) {
> > g_free(nd->model);
> > @@ -1928,7 +1899,33 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
> > exit(1);
> > }
> >
> > - bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
> > + if (!rootbus) {
> > + error_report("No primary PCI bus");
> > + exit(1);
> > + }
> > +
> > + assert(!rootbus->parent_dev);
> > +
> > + if (!devaddr) {
> > + devfn = -1;
> > + busnr = 0;
> > + bus = pci_find_bus_nr(rootbus, 0);
>
> This line isn't needed since it is done below...
Oops, missed that when I factored the find_bus_nr out of the if.
Fixed now.
> > + } else {
> > + if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) {
> > + error_report("Invalid PCI device address %s for device %s",
> > + devaddr, nd->model);
> > + exit(1);
> > + }
> > +
> > + if (dom != 0) {
> > + error_report("No support for non-zero PCI domains");
> > + exit(1);
> > + }
> > +
> > + devfn = PCI_DEVFN(slot, 0);
> > + }
> > +
> > + bus = pci_find_bus_nr(rootbus, busnr);
>
> ... here.
>
> > if (!bus) {
> > error_report("Invalid PCI device address %s for device %s",
> > devaddr, nd->model);
>
> Maybe output a different message from the one for pci_parse_devaddr()
> failures ? Here, the address is supposed to be well formatted but we
> couldn't find the requested bus.
I thought about that, but couldn't think of a could way of expressing
it. Since this is only for a legacy option and it was already
ambiguous, I'm not overly concerned by it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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