From: Jonathan Behrens <jonathan@fintelia.io>
To: qemu-devel@nongnu.org
Cc: Jonathan Behrens <jonathan@fintelia.io>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-riscv@nongnu.org, Jonathan Behrens <fintelia@gmail.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes
Date: Wed, 8 May 2019 13:38:35 -0400 [thread overview]
Message-ID: <20190508173835.14528-1-jonathan@fintelia.io> (raw)
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -732,7 +732,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--
2.20.1
next reply other threads:[~2019-05-08 17:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-08 17:38 Jonathan Behrens [this message]
2019-05-08 17:47 ` [Qemu-devel] [PATCH] target/riscv: Only flush TLB if SATP.ASID changes Richard Henderson
2019-05-08 20:17 ` Alistair Francis
2019-05-08 20:42 ` Palmer Dabbelt
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