From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault
Date: Wed, 8 May 2019 23:02:30 -0700 [thread overview]
Message-ID: <20190509060246.4031-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190509060246.4031-1-richard.henderson@linaro.org>
Since the only non-negative TLBRET_* value is TLBRET_MATCH,
the subsequent test for ret < 0 is useless. Use early return
to allow subsequent blocks to be unindented.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/helper.c | 54 ++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index cc7be7703a..86e622efb8 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -915,41 +915,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- } else if (ret < 0)
-#endif
- {
-#if !defined(CONFIG_USER_ONLY)
+ return 0;
+ }
#if !defined(TARGET_MIPS64)
- if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
- /*
- * Memory reads during hardware page table walking are performed
- * as if they were kernel-mode load instructions.
- */
- int mode = (env->hflags & MIPS_HFLAG_KSU);
- bool ret_walker;
- env->hflags &= ~MIPS_HFLAG_KSU;
- ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
- env->hflags |= mode;
- if (ret_walker) {
- ret = get_physical_address(env, &physical, &prot,
- address, rw, access_type, mmu_idx);
- if (ret == TLBRET_MATCH) {
- tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
- mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- return ret;
- }
+ if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
+ /*
+ * Memory reads during hardware page table walking are performed
+ * as if they were kernel-mode load instructions.
+ */
+ int mode = (env->hflags & MIPS_HFLAG_KSU);
+ bool ret_walker;
+ env->hflags &= ~MIPS_HFLAG_KSU;
+ ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
+ env->hflags |= mode;
+ if (ret_walker) {
+ ret = get_physical_address(env, &physical, &prot,
+ address, rw, access_type, mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ mmu_idx, TARGET_PAGE_SIZE);
+ return 0;
}
}
-#endif
-#endif
- raise_mmu_exception(env, address, rw, ret);
- ret = 1;
}
+#endif
+#endif
- return ret;
+ raise_mmu_exception(env, address, rw, ret);
+ return 1;
}
#if !defined(CONFIG_USER_ONLY)
--
2.17.1
next prev parent reply other threads:[~2019-05-09 6:14 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-09 6:02 [Qemu-devel] [PATCH v2 00/27] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 01/27] " Richard Henderson
2019-05-09 17:39 ` Alistair Francis
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 02/27] target/alpha: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 03/27] target/arm: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 04/27] target/cris: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 05/27] target/hppa: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 06/27] target/i386: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 07/27] target/lm32: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 08/27] target/m68k: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 09/27] target/microblaze: " Richard Henderson
2019-05-09 9:59 ` Peter Maydell
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only Richard Henderson
2019-05-09 9:45 ` Philippe Mathieu-Daudé
2019-05-09 6:02 ` Richard Henderson [this message]
2019-05-09 10:01 ` [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault Philippe Mathieu-Daudé
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 12/27] target/mips: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09 9:50 ` Philippe Mathieu-Daudé
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 13/27] target/moxie: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 14/27] target/nios2: " Richard Henderson
2019-05-09 10:02 ` Peter Maydell
2019-05-09 15:43 ` Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 15/27] target/openrisc: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 16/27] target/ppc: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 17/27] target/riscv: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 18/27] target/s390x: " Richard Henderson
2019-05-09 7:04 ` David Hildenbrand
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 19/27] target/sh4: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 20/27] target/sparc: " Richard Henderson
2019-05-09 13:35 ` Peter Maydell
2019-05-09 15:51 ` Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 21/27] target/tilegx: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 22/27] target/tricore: " Richard Henderson
2019-05-09 9:43 ` Bastian Koppelmann
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 23/27] target/unicore32: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 24/27] target/xtensa: " Richard Henderson
2019-05-09 9:56 ` Peter Maydell
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 26/27] tcg: Remove CPUClass::handle_mmu_fault Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-05-09 9:56 ` Philippe Mathieu-Daudé
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