From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [Qemu-devel] [PATCH v2 22/27] target/tricore: Convert to CPUClass::tlb_fill
Date: Wed, 8 May 2019 23:02:41 -0700 [thread overview]
Message-ID: <20190509060246.4031-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190509060246.4031-1-richard.henderson@linaro.org>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/cpu.h | 6 +++---
target/tricore/cpu.c | 1 +
target/tricore/helper.c | 27 +++++++++++++++++++--------
target/tricore/op_helper.c | 26 --------------------------
4 files changed, 23 insertions(+), 37 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 64d1a9c75e..287f4328a3 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -417,8 +417,8 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
#define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
/* helpers.c */
-int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
- int rw, int mmu_idx);
-#define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
+bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
#endif /* TRICORE_CPU_H */
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index e8d37e4040..ea1199d27e 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -166,6 +166,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_attrs_debug = tricore_cpu_get_phys_page_attrs_debug;
cc->tcg_initialize = tricore_tcg_init;
+ cc->tlb_fill = tricore_cpu_tlb_fill;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 78ee87c9ea..ed184fee3a 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -50,8 +50,9 @@ static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
{
}
-int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
- int rw, int mmu_idx)
+bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType rw, int mmu_idx,
+ bool probe, uintptr_t retaddr)
{
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;
@@ -64,20 +65,30 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
- qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
- " prot %d\n", __func__, address, ret, physical, prot);
+
+ qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
+ TARGET_FMT_plx " prot %d\n",
+ __func__, (target_ulong)address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- } else if (ret < 0) {
+ return true;
+ } else {
+ assert(ret < 0);
+ if (probe) {
+ return false;
+ }
raise_mmu_exception(env, address, rw, ret);
- ret = 1;
+ cpu_loop_exit_restore(cs, retaddr);
}
+}
- return ret;
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+ tricore_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index ed9dc0c83e..601e92f92a 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2793,29 +2793,3 @@ uint32_t helper_psw_read(CPUTriCoreState *env)
{
return psw_read(env);
}
-
-
-static inline void QEMU_NORETURN do_raise_exception_err(CPUTriCoreState *env,
- uint32_t exception,
- int error_code,
- uintptr_t pc)
-{
- CPUState *cs = CPU(tricore_env_get_cpu(env));
- cs->exception_index = exception;
- env->error_code = error_code;
- /* now we have a real cpu fault */
- cpu_loop_exit_restore(cs, pc);
-}
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
- int ret;
- ret = cpu_tricore_handle_mmu_fault(cs, addr, access_type, mmu_idx);
- if (ret) {
- TriCoreCPU *cpu = TRICORE_CPU(cs);
- CPUTriCoreState *env = &cpu->env;
- do_raise_exception_err(env, cs->exception_index,
- env->error_code, retaddr);
- }
-}
--
2.17.1
next prev parent reply other threads:[~2019-05-09 6:23 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-09 6:02 [Qemu-devel] [PATCH v2 00/27] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 01/27] " Richard Henderson
2019-05-09 17:39 ` Alistair Francis
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 02/27] target/alpha: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 03/27] target/arm: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 04/27] target/cris: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 05/27] target/hppa: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 06/27] target/i386: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 07/27] target/lm32: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 08/27] target/m68k: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 09/27] target/microblaze: " Richard Henderson
2019-05-09 9:59 ` Peter Maydell
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only Richard Henderson
2019-05-09 9:45 ` Philippe Mathieu-Daudé
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault Richard Henderson
2019-05-09 10:01 ` Philippe Mathieu-Daudé
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 12/27] target/mips: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09 9:50 ` Philippe Mathieu-Daudé
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 13/27] target/moxie: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 14/27] target/nios2: " Richard Henderson
2019-05-09 10:02 ` Peter Maydell
2019-05-09 15:43 ` Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 15/27] target/openrisc: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 16/27] target/ppc: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 17/27] target/riscv: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 18/27] target/s390x: " Richard Henderson
2019-05-09 7:04 ` David Hildenbrand
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 19/27] target/sh4: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 20/27] target/sparc: " Richard Henderson
2019-05-09 13:35 ` Peter Maydell
2019-05-09 15:51 ` Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 21/27] target/tilegx: " Richard Henderson
2019-05-09 6:02 ` Richard Henderson [this message]
2019-05-09 9:43 ` [Qemu-devel] [PATCH v2 22/27] target/tricore: " Bastian Koppelmann
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 23/27] target/unicore32: " Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 24/27] target/xtensa: " Richard Henderson
2019-05-09 9:56 ` Peter Maydell
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 26/27] tcg: Remove CPUClass::handle_mmu_fault Richard Henderson
2019-05-09 6:02 ` [Qemu-devel] [PATCH v2 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-05-09 9:56 ` Philippe Mathieu-Daudé
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