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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 26/27] tcg: Remove CPUClass::handle_mmu_fault
Date: Wed,  8 May 2019 23:02:45 -0700	[thread overview]
Message-ID: <20190509060246.4031-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190509060246.4031-1-richard.henderson@linaro.org>

This hook is now completely replaced by tlb_fill.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/qom/cpu.h     |  3 ---
 accel/tcg/user-exec.c | 13 +++----------
 2 files changed, 3 insertions(+), 13 deletions(-)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index c1f267b4e0..32983f27c3 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -117,7 +117,6 @@ struct TranslationBlock;
  *       This always includes at least the program counter; some targets
  *       will need to do more. If this hook is not implemented then the
  *       default is to call @set_pc(tb->pc).
- * @handle_mmu_fault: Callback for handling an MMU fault.
  * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
  *       address fault.  For system mode, if the access is valid, call
  *       tlb_set_page and return true; if the access is invalid, and
@@ -195,8 +194,6 @@ typedef struct CPUClass {
                                Error **errp);
     void (*set_pc)(CPUState *cpu, vaddr value);
     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
-    int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw,
-                            int mmu_index);
     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
                      MMUAccessType access_type, int mmu_idx,
                      bool probe, uintptr_t retaddr);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 199f88c826..8cfbeb1b56 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -63,7 +63,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
 {
     CPUState *cpu = current_cpu;
     CPUClass *cc;
-    int ret;
     unsigned long address = (unsigned long)info->si_addr;
     MMUAccessType access_type;
 
@@ -156,15 +155,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
     helper_retaddr = 0;
 
     cc = CPU_GET_CLASS(cpu);
-    if (cc->tlb_fill) {
-        access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
-        cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
-        g_assert_not_reached();
-    } else {
-        ret = cc->handle_mmu_fault(cpu, address, 0, is_write, MMU_USER_IDX);
-        g_assert(ret > 0);
-        cpu_loop_exit_restore(cpu, pc);
-    }
+    access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
+    cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+    g_assert_not_reached();
 }
 
 #if defined(__i386__)
-- 
2.17.1



  parent reply	other threads:[~2019-05-09  6:23 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-09  6:02 [Qemu-devel] [PATCH v2 00/27] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 01/27] " Richard Henderson
2019-05-09 17:39   ` Alistair Francis
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 02/27] target/alpha: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 03/27] target/arm: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 04/27] target/cris: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 05/27] target/hppa: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 06/27] target/i386: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 07/27] target/lm32: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 08/27] target/m68k: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 09/27] target/microblaze: " Richard Henderson
2019-05-09  9:59   ` Peter Maydell
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only Richard Henderson
2019-05-09  9:45   ` Philippe Mathieu-Daudé
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault Richard Henderson
2019-05-09 10:01   ` Philippe Mathieu-Daudé
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 12/27] target/mips: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-09  9:50   ` Philippe Mathieu-Daudé
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 13/27] target/moxie: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 14/27] target/nios2: " Richard Henderson
2019-05-09 10:02   ` Peter Maydell
2019-05-09 15:43     ` Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 15/27] target/openrisc: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 16/27] target/ppc: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 17/27] target/riscv: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 18/27] target/s390x: " Richard Henderson
2019-05-09  7:04   ` David Hildenbrand
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 19/27] target/sh4: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 20/27] target/sparc: " Richard Henderson
2019-05-09 13:35   ` Peter Maydell
2019-05-09 15:51     ` Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 21/27] target/tilegx: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 22/27] target/tricore: " Richard Henderson
2019-05-09  9:43   ` Bastian Koppelmann
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 23/27] target/unicore32: " Richard Henderson
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 24/27] target/xtensa: " Richard Henderson
2019-05-09  9:56   ` Peter Maydell
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-05-09  6:02 ` Richard Henderson [this message]
2019-05-09  6:02 ` [Qemu-devel] [PATCH v2 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-05-09  9:56   ` Philippe Mathieu-Daudé

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