From: David Gibson <david@gibson.dropbear.id.au>
To: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Cc: groug@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org
Subject: Re: [Qemu-devel] [QEMU-PPC] [PATCH 05/13] target/ppc: Add privileged message send facilities
Date: Fri, 10 May 2019 12:09:09 +1000 [thread overview]
Message-ID: <20190510020909.GA20559@umbus.fritz.box> (raw)
In-Reply-To: <20190503055316.6441-6-sjitindarsingh@gmail.com>
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On Fri, May 03, 2019 at 03:53:08PM +1000, Suraj Jitindar Singh wrote:
> Privileged message send facilities exist on POWER8 processors and later
> and include a register and instructions which can be used to generate,
> observe/modify the state of and clear privileged doorbell exceptions as
> described below.
>
> The Directed Privileged Doorbell Exception State (DPDES) register
> reflects the state of pending privileged doorbell exceptions and can
> also be used to modify that state. The register can be used to read and
> modify the state of privileged doorbell exceptions for all threads of a
> subprocessor and thus is a shared facility for that subprocessor. The
> register can be read/written by the hypervisor and read by the
> supervisor if enabled in the HFSCR, otherwise a hypervisor facility
> unavailable exception is generated.
>
> The privileged message send and clear instructions (msgsndp & msgclrp)
> are used to generate and clear the presence of a directed privileged
> doorbell exception, respectively. The msgsndp instruction can be used to
> target any thread of the current subprocessor, msgclrp acts on the
> thread issuing the instruction. These instructions are privileged, but
> will generate a hypervisor facility unavailable exception if not enabled
> in the HFSCR and executed in privileged non-hypervisor state.
>
> Add and implement this register and instructions by reading or modifying the
> pending interrupt state of the cpu.
>
> Note that TCG only supports one thread per core and so we only need to
> worry about the cpu making the access.
>
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
I think this would be clearer if you put the framework for the
facility unavailable exception into a separate patch. Apart from
that, LGTM.
> ---
> target/ppc/cpu.h | 7 +++++
> target/ppc/excp_helper.c | 63 +++++++++++++++++++++++++++++++++++++----
> target/ppc/helper.h | 5 ++++
> target/ppc/misc_helper.c | 46 ++++++++++++++++++++++++++++++
> target/ppc/translate.c | 28 ++++++++++++++++++
> target/ppc/translate_init.inc.c | 40 ++++++++++++++++++++++++++
> 6 files changed, 184 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index e324064111..1d2a088391 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -425,6 +425,10 @@ typedef struct ppc_v3_pate_t {
> #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
> #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
>
> +/* HFSCR bits */
> +#define HFSCR_MSGSNDP PPC_BIT(53) /* Privileged Message Send Facilities */
> +#define HFSCR_IC_MSGSNDP 0xA
> +
> #define msr_sf ((env->msr >> MSR_SF) & 1)
> #define msr_isf ((env->msr >> MSR_ISF) & 1)
> #define msr_shv ((env->msr >> MSR_SHV) & 1)
> @@ -1355,6 +1359,8 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
> #endif
>
> void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
> +void gen_hfscr_facility_check(DisasContext *ctx, int facility_sprn, int bit,
> + int sprn, int cause);
>
> static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
> {
> @@ -1501,6 +1507,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
> #define SPR_MPC_ICTRL (0x09E)
> #define SPR_MPC_BAR (0x09F)
> #define SPR_PSPB (0x09F)
> +#define SPR_DPDES (0x0B0)
> #define SPR_DAWR (0x0B4)
> #define SPR_RPR (0x0BA)
> #define SPR_CIABR (0x0BB)
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index beafcf1ebd..7a4da7bdba 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -461,6 +461,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> #endif
> break;
> + case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> + env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> + srr0 = SPR_HSRR0;
> + srr1 = SPR_HSRR1;
> + new_msr |= (target_ulong)MSR_HVB;
> + new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> LOG_EXCP("PIT exception\n");
> break;
> @@ -884,7 +891,11 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> }
> if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
> env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
> - powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
> + if (env->insns_flags & PPC_SEGMENT_64B) {
> + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR);
> + } else {
> + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
> + }
> return;
> }
> if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) {
> @@ -1202,19 +1213,26 @@ void helper_msgsnd(target_ulong rb)
> }
>
> /* Server Processor Control */
> -static int book3s_dbell2irq(target_ulong rb)
> +static int book3s_dbell2irq(target_ulong rb, bool hv_dbell)
> {
> int msg = rb & DBELL_TYPE_MASK;
>
> /* A Directed Hypervisor Doorbell message is sent only if the
> * message type is 5. All other types are reserved and the
> * instruction is a no-op */
> - return msg == DBELL_TYPE_DBELL_SERVER ? PPC_INTERRUPT_HDOORBELL : -1;
> + if (msg == DBELL_TYPE_DBELL_SERVER) {
> + if (hv_dbell)
> + return PPC_INTERRUPT_HDOORBELL;
> + else
> + return PPC_INTERRUPT_DOORBELL;
> + }
> +
> + return -1;
> }
>
> void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
> {
> - int irq = book3s_dbell2irq(rb);
> + int irq = book3s_dbell2irq(rb, 1);
>
> if (irq < 0) {
> return;
> @@ -1225,7 +1243,42 @@ void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb)
>
> void helper_book3s_msgsnd(target_ulong rb)
> {
> - int irq = book3s_dbell2irq(rb);
> + int irq = book3s_dbell2irq(rb, 1);
> + int pir = rb & DBELL_PROCIDTAG_MASK;
> + CPUState *cs;
> +
> + if (irq < 0) {
> + return;
> + }
> +
> + qemu_mutex_lock_iothread();
> + CPU_FOREACH(cs) {
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *cenv = &cpu->env;
> +
> + /* TODO: broadcast message to all threads of the same processor */
> + if (cenv->spr_cb[SPR_PIR].default_value == pir) {
> + cenv->pending_interrupts |= 1 << irq;
> + cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> + }
> + }
> + qemu_mutex_unlock_iothread();
> +}
> +
> +void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
> +{
> + int irq = book3s_dbell2irq(rb, 0);
> +
> + if (irq < 0) {
> + return;
> + }
> +
> + env->pending_interrupts &= ~(1 << irq);
> +}
> +
> +void helper_book3s_msgsndp(target_ulong rb)
> +{
> + int irq = book3s_dbell2irq(rb, 0);
> int pir = rb & DBELL_PROCIDTAG_MASK;
> CPUState *cs;
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 6aee195528..040f59d1af 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -657,6 +657,8 @@ DEF_HELPER_1(msgsnd, void, tl)
> DEF_HELPER_2(msgclr, void, env, tl)
> DEF_HELPER_1(book3s_msgsnd, void, tl)
> DEF_HELPER_2(book3s_msgclr, void, env, tl)
> +DEF_HELPER_1(book3s_msgsndp, void, tl)
> +DEF_HELPER_2(book3s_msgclrp, void, env, tl)
> #endif
>
> DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32)
> @@ -674,6 +676,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
>
> DEF_HELPER_2(load_dump_spr, void, env, i32)
> DEF_HELPER_2(store_dump_spr, void, env, i32)
> +DEF_HELPER_4(hfscr_facility_check, void, env, i32, i32, i32)
> DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
> DEF_HELPER_4(msr_facility_check, void, env, i32, i32, i32)
> DEF_HELPER_FLAGS_1(load_tbl, TCG_CALL_NO_RWG, tl, env)
> @@ -688,6 +691,8 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
> DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
> DEF_HELPER_FLAGS_2(store_purr, TCG_CALL_NO_RWG, void, env, tl)
> DEF_HELPER_2(store_ptcr, void, env, tl)
> +DEF_HELPER_FLAGS_1(load_dpdes, TCG_CALL_NO_RWG, tl, env)
> +DEF_HELPER_FLAGS_2(store_dpdes, TCG_CALL_NO_RWG, void, env, tl)
> #endif
> DEF_HELPER_2(store_sdr1, void, env, tl)
> DEF_HELPER_2(store_pidr, void, env, tl)
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index c65d1ade15..d7d4acca7f 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -39,6 +39,17 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
> }
>
> #ifdef TARGET_PPC64
> +static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
> + uint32_t sprn, uint32_t cause,
> + uintptr_t raddr)
> +{
> + qemu_log("Facility SPR %d is unavailable (SPR HFSCR:%d)\n", sprn, bit);
> +
> + env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
> +
> + raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
> +}
> +
> static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
> uint32_t sprn, uint32_t cause,
> uintptr_t raddr)
> @@ -53,6 +64,17 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
> }
> #endif
>
> +void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
> + uint32_t sprn, uint32_t cause)
> +{
> +#ifdef TARGET_PPC64
> + if ((env->msr_mask & MSR_HVB) && !msr_hv &&
> + !(env->spr[SPR_HFSCR] & (1UL << bit))) {
> + raise_hv_fu_exception(env, bit, sprn, cause, GETPC());
> + }
> +#endif
> +}
> +
> void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
> uint32_t sprn, uint32_t cause)
> {
> @@ -107,6 +129,30 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value)
>
> env->spr[SPR_PCR] = value & pcc->pcr_mask;
> }
> +
> +target_ulong helper_load_dpdes(CPUPPCState *env)
> +{
> + helper_hfscr_facility_check(env, HFSCR_MSGSNDP, SPR_DPDES,
> + HFSCR_IC_MSGSNDP);
> +
> + if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL))
> + return 1;
> + return 0;
> +}
> +
> +void helper_store_dpdes(CPUPPCState *env, target_ulong val)
> +{
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + if (val) {
> + /* Only one cpu for now */
> + env->pending_interrupts |= 1 << PPC_INTERRUPT_DOORBELL;
> + cpu_interrupt(cs, CPU_INTERRUPT_HARD);
> + } else {
> + env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
> + }
> +}
> #endif /* defined(TARGET_PPC64) */
>
> void helper_store_pidr(CPUPPCState *env, target_ulong val)
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index fb42585a1c..2c3e83d18e 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -6537,6 +6537,30 @@ static void gen_msgsnd(DisasContext *ctx)
> #endif /* defined(CONFIG_USER_ONLY) */
> }
>
> +static void gen_msgclrp(DisasContext *ctx)
> +{
> +#if defined(CONFIG_USER_ONLY)
> + GEN_PRIV;
> +#else
> + CHK_SV;
> + gen_hfscr_facility_check(ctx, SPR_HFSCR, HFSCR_MSGSNDP, 0,
> + HFSCR_IC_MSGSNDP);
> + gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
> +#endif /* defined(CONFIG_USER_ONLY) */
> +}
> +
> +static void gen_msgsndp(DisasContext *ctx)
> +{
> +#if defined(CONFIG_USER_ONLY)
> + GEN_PRIV;
> +#else
> + CHK_SV;
> + gen_hfscr_facility_check(ctx, SPR_HFSCR, HFSCR_MSGSNDP, 0,
> + HFSCR_IC_MSGSNDP);
> + gen_helper_book3s_msgsndp(cpu_gpr[rB(ctx->opcode)]);
> +#endif /* defined(CONFIG_USER_ONLY) */
> +}
> +
> static void gen_msgsync(DisasContext *ctx)
> {
> #if defined(CONFIG_USER_ONLY)
> @@ -7054,6 +7078,10 @@ GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
> PPC_NONE, PPC2_PRCNTL),
> GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
> PPC_NONE, PPC2_PRCNTL),
> +GEN_HANDLER2_E(msgsndp, "msgsndp", 0x1F, 0x0E, 0x04, 0x03ff0001,
> + PPC_NONE, PPC2_ISA207S),
> +GEN_HANDLER2_E(msgclrp, "msgclrp", 0x1F, 0x0E, 0x05, 0x03ff0001,
> + PPC_NONE, PPC2_ISA207S),
> GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
> GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
> GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 8e287066e5..46f9399097 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -454,6 +454,19 @@ static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
> {
> gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
> }
> +
> +/* DPDES */
> +static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
> +{
> + gen_hfscr_facility_check(ctx, SPR_HFSCR, HFSCR_MSGSNDP, sprn,
> + HFSCR_IC_MSGSNDP);
> + gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
> +}
> +
> +static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
> +{
> + gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
> +}
> #endif
> #endif
>
> @@ -7478,6 +7491,20 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
> #define POWERPC970_HID5_INIT 0x00000000
> #endif
>
> +void gen_hfscr_facility_check(DisasContext *ctx, int facility_sprn, int bit,
> + int sprn, int cause)
> +{
> + TCGv_i32 t1 = tcg_const_i32(bit);
> + TCGv_i32 t2 = tcg_const_i32(sprn);
> + TCGv_i32 t3 = tcg_const_i32(cause);
> +
> + gen_helper_hfscr_facility_check(cpu_env, t1, t2, t3);
> +
> + tcg_temp_free_i32(t3);
> + tcg_temp_free_i32(t2);
> + tcg_temp_free_i32(t1);
> +}
> +
> static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> int bit, int sprn, int cause)
> {
> @@ -8249,6 +8276,17 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
> #endif
> }
>
> +static void gen_spr_power8_dpdes(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> + spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_dpdes, SPR_NOACCESS,
> + &spr_read_dpdes, &spr_write_dpdes,
> + KVM_REG_PPC_DPDES, 0x0UL);
> +#endif
> +}
> +
> static void gen_spr_power9_mmu(CPUPPCState *env)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -8637,6 +8675,7 @@ static void init_proc_POWER8(CPUPPCState *env)
> gen_spr_power8_ic(env);
> gen_spr_power8_book4(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power8_dpdes(env);
>
> /* env variables */
> env->dcache_line_size = 128;
> @@ -8826,6 +8865,7 @@ static void init_proc_POWER9(CPUPPCState *env)
> gen_spr_power8_ic(env);
> gen_spr_power8_book4(env);
> gen_spr_power8_rpr(env);
> + gen_spr_power8_dpdes(env);
> gen_spr_power9_mmu(env);
>
> /* POWER9 Specific registers */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2019-05-10 3:04 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-03 5:53 [Qemu-devel] [QEMU-PPC] [PATCH 00/13] target/ppc: Implement KVM support under TCG Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 01/13] target/ppc: Implement the VTB for HV access Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-06 6:02 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 02/13] target/ppc: Work [S]PURR implementation and add HV support Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-06 6:15 ` David Gibson
2019-05-07 1:28 ` Suraj Jitindar Singh
2019-05-09 6:45 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 03/13] target/ppc: Add SPR ASDR Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-06 6:16 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 04/13] target/ppc: Add SPR TBU40 Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-06 6:17 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 05/13] target/ppc: Add privileged message send facilities Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 2:09 ` David Gibson [this message]
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 06/13] target/ppc: Enforce that the root page directory size must be at least 5 Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 2:11 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 07/13] target/ppc: Handle partition scoped radix tree translation Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 2:28 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 08/13] target/ppc: Implement hcall H_SET_PARTITION_TABLE Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 2:30 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 09/13] target/ppc: Implement hcall H_ENTER_NESTED Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 2:57 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 10/13] target/ppc: Implement hcall H_TLB_INVALIDATE Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 6:28 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 11/13] target/ppc: Implement hcall H_COPY_TOFROM_GUEST Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 6:32 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 12/13] target/ppc: Introduce POWER9 DD2.2 cpu type Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 6:32 ` David Gibson
2019-05-03 5:53 ` [Qemu-devel] [QEMU-PPC] [PATCH 13/13] target/ppc: Enable SPAPR_CAP_NESTED_KVM_HV under tcg Suraj Jitindar Singh
2019-05-03 5:53 ` Suraj Jitindar Singh
2019-05-10 6:34 ` David Gibson
2019-05-03 5:58 ` [Qemu-devel] [QEMU-PPC] [PATCH 00/13] target/ppc: Implement KVM support under TCG Suraj Jitindar Singh
2019-05-03 5:58 ` Suraj Jitindar Singh
2019-05-06 6:20 ` David Gibson
2019-05-06 23:45 ` Suraj Jitindar Singh
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